Implementation efficient digital picture-in-picture decoding methods and apparatus

• US 5,828,421 A
• Filed: 06/06/1995
• Issued: 10/27/1998
• Est. Priority Date: 10/11/1994
• Status: Expired due to Term

• Current Assignee: Hitachi America Limited (Hitachi, Ltd.)
• Original Assignee: Hitachi America Limited (Hitachi, Ltd.)
• Inventors: Boyce, Jill MacDonald, Pearlstein, Larry, Lane, Frank Anton
• Primary Examiner(s): Casler, Brian
• Assistant Examiner(s): DIN, LUANNE PAN
• Application Number:
  US08/468,147
• Time in Patent Office: 1,239 Days
• Field of Search: 348/565, 348/566, 348/567, 348/568, 348/399, 348/403, 348/420, 348/424, 348/409-416
• US Class Current: 348/565
• CPC Class Codes: G06T 3/4084 in the transform domain, e.g. fast Fourier transform [FFT] domain scaling
• CPC Class Codes: H04N 19/122 Selection of transform size, e.g. 8x8 or 2x4x8 DCT; Selection of sub-band transforms of varying structure or type
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/132 Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
• CPC Class Codes: H04N 19/159 Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
• CPC Class Codes: H04N 19/162 User input
• CPC Class Codes: H04N 19/172 the region being a picture, frame or field
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/18 the unit being a set of transform coefficients
• CPC Class Codes: H04N 19/184 the unit being bits, e.g. of the compressed video stream
• CPC Class Codes: H04N 19/30 using hierarchical techniques, e.g. scalability H04N19/63 takes precedence
• CPC Class Codes: H04N 19/40 using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/427 Display on the fly, e.g. simultaneous writing to and reading from decoding memory
• CPC Class Codes: H04N 19/428 Recompression, e.g. by spatial or temporal decimation
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/48 using compressed domain processing techniques other than decoding, e.g. modification of transform coefficients, variable length coding [VLC] data or run-length data motion estimation in a transform domain H04N19/547; processing of decoded motion vectors H04N19/513
• CPC Class Codes: H04N 19/59 involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 : Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/440254 : by altering signal-to-noise parameters, e.g. requantization
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27

Abstract

An implementation efficient video decoder suitable for use as a picture in picture decoder is described. In one embodiment, the video decoder receives primary and secondary bitstreams with the secondary bitstream including the video data intended to be displayed as inset pictures. The decoder uses many of the same circuit components on a time shared basis to decode both the main and inset pictures reducing the amount of circuitry required to implement the decoder. In one embodiment a preparser discards the majority of DCT coefficients in the secondary bitstream and the remaining data is variable length decoded and then variable length encoded using a non-MPEG compliant coding scheme prior to storing the inset picture data in a coded data buffer. Re-encoding of the selected inset picture data in this manner greatly reduces data storage requirements and simplifies the circuitry required to subsequently decode the inset picture data. To reduce frame memory requirements inset picture data is downsampled, stored and then upsampled prior to display thereby reducing inset picture frame memory buffer requirements.

Claims

1. A picture-in-picture decoder circuit, comprising:

memory for storing main picture data and inset picture data representing first and second images, respectively; and

time shared decoding circuit means, coupled to the memory, for decoding the main and inset picture data stored in the memory device in a period of time equal to or less than the time used to display a picture, the time shared decoding circuit means including at least some common circuitry that is used on a time shared basis to decode the main and inset picture data.

2. The picture-in-picture decoder circuit of claim 1, further comprising:

preparser means coupled to the memory device for receiving and discarding a majority of the received inset picture data prior to the inset picture data being stored in the memory device.

3. The picture-in-picture decoder circuit of claim 1, wherein the inset picture data includes video blocks represented by a plurality of discrete cosine transform coefficients and wherein the picture in picture decoder circuit further includes:

means for discarding a majority of the discrete cosine transform coefficients included in each video block of the inset picture data;

means for variable length decoding the inset picture data; and

means for re-encoding the inset picture data using less than 16 discrete cosine transform coefficients for each video data block.

4. The picture-in-picture decoder circuit of claim 3,

wherein said means storing main picture and inset picture data is implemented as a single memory unit.

5. The picture-in-picture decoder circuit of claim 1, wherein the common circuitry included in the time shared decoding circuit means includes:

an inverse discrete cosine transform circuit that is used in decoding both the main and inset picture data.

6. A method of decoding digital video data representing a main picture and an inset picture, the method comprising the steps of:

receiving encoded main picture video data;

receiving encoded inset picture data;

operating a preparser to selectively discard the majority of the received inset picture data;

storing the encoded main picture data and inset picture data in a common memory unit by transporting the main picture data and inset picture data over a bus; and

operating a preparser to discard a minority of the encoded main picture data during periods of peak demands for transporting data over the bus.

7. The method of claim 6, further comprising the step of:

performing unidirectional motion compensated predication on bi-directionally encoded main picture data.

8. A method of processing first and second sets of picture data, one of the first and second sets of picture data representing inset picture data, the method comprising the steps of:

storing the first and second sets of picture data;

decoding the first and second sets of picture data in a period of time equal to or less than the time used to display a picture represented by the first set of picture data, the step of decoding the first and second sets of picture data including the steps of;

i. decoding the first set of picture data using a first set of circuitry;

ii. decoding the second set of picture data using, on a time shared basis, at least some circuitry included in the first set of circuitry that was used to decode the first set of picture data; and

using one of the decoded first and second sets of picture data as inset picture data.

9. The method of claim 8, wherein the at least some circuitry, that was used to decode the first set of picture data, includes an inverse discrete cosine transform circuit.