Power-up circuit for field programmable gate arrays

• US 5,828,538 A
• Filed: 01/03/1997
• Issued: 10/27/1998
• Est. Priority Date: 06/21/1996
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Chan, Andrew K., Apland, James M.
• Primary Examiner(s): Leja, Ronald W.
• Application Number:
  US08/775,984
• Time in Patent Office: 662 Days
• Field of Search: 361/18, 361/56, 361/78, 361/86, 361/88, 361/90-92, 361/110, 326/33, 326/39
• US Class Current: 361/56
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 19/17772 for powering on or off
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module'"'"'s internal disable input.

Claims

1. A protection circuit for preventing a current spike in a logic module having an internal disable input during power up of a field programmable gate array, the protection circuit comprising means for providing a voltage input to the internal disable input to disable the logic module until a voltage output by a charge pump of the field programmable gate array reaches a predetermined voltage, the voltage input to the internal disable input being substantially equal to an instantaneous supply voltage being applied to the protection circuit, the means for providing comprising:

means for providing an increasing voltage proportional to the voltage output by the charge pump to the protection circuit at a first node of the protection circuit during power up;

means for retarding the voltage increase at the first node of the protection circuit during power up;

means for providing a voltage at a second node substantially equal to the instantaneous supply voltage being applied to the protection circuit during power up; and

means for switching the voltage input to the internal disable input from a digital logic high to a digital logic low.

2. The protection circuit of claim 1, wherein the means for switching the voltage input to the internal disable input comprises a first inverter disposed between the first node and the second node, wherein the inverter switches when the voltage at the first node reaches the switching threshold voltage of the first inverter.

3. The protection circuit of claim 2, further comprising means for communicating the voltage at the second node to the internal disable input.

4. The protection circuit of claim 3, wherein the means for communicating the voltage at the second node to the internal disable input comprises a buffer circuit with hysteresis.

5. The protection circuit of claim 4, wherein the means for communicating the voltage at the second node to the internal disable input further comprises a buffer.

6. The protection circuit of claim 5, wherein the buffer circuit with hysteresis comprises a second and third inverter disposed between the second node and the buffer and a transistor disposed between the second node and ground with a gate connected to a third node between the second and third inverter.

7. A method of preventing a current spike in a logic module having an internal disable input during power up of a field programmable gate array, the method comprising:

inputting a voltage to the internal disable input to disable the logic module until a voltage output by a charge pump of the field programmable gate array reaches a predetermined voltage, wherein the voltage input to the internal disable input is substantially equal to an instantaneous voltage being applied to the logic module;

providing an increasing voltage proportional to the voltage output by the charge pump to an input of a first inverter;

retarding the increasing voltage at the input of the first inverter;

providing a voltage at the output of the first inverter which is substantially equal to an instantaneous supply voltage being applied to the logic module during power up; and

switching the voltage input to the internal disable input from a digital logic high to a digital logic low.

8. The method of claim 7, further comprising communicating the voltage at the output of the first inverter to the internal disable input.

9. A field programmable gate array, comprising:

an interconnect structure comprising routing conductors;

a plurality of logic modules, each of the logic modules having an input logic element, the input logic element having a plurality of inputs which when the field programmable gate array is unconfigured are not coupled to an output of any logic module, the input logic element also having an internal disable input; and

a protection circuit having an output coupled to the internal disable inputs of the logic modules and supplying a first voltage signal onto the internal disable inputs during a first power up period and supplying a second voltage signal onto the internal disable inputs during a second power up period, the second power up period starting before a supply voltage VCC of the field programmable gate array reaches steady state.

10. A field programmable gate array, comprising:

an interconnect structure comprising routing conductors;

a plurality of logic modules, each of the logic modules having an input logic element, the input logic element having a plurality of inputs which when the field programmable gate array is unconfigured are not coupled to an output of any logic module, the input logic element also having an internal disable input;

a protection circuit having an output coupled to the internal disable inputs of the logic modules and supplying a first voltage signal onto the internal disable inputs during a first power up period and supplying a second voltage signal onto the internal disable inputs during a second power up period, the second power up period starting before a supply voltage VCC of the field programmable gate array reaches steady state; and

a charge pump, the second power up period starting when a voltage output by the charge pump reaches a predetermined voltage.

11. A field programmable gate array, comprising:

an interconnect structure comprising routing conductors;

a plurality of logic modules, each of the logic modules having an input logic element, the input logic element having a plurality of inputs which when the field programmable gate array is unconfigured are not coupled to an output of any logic module, the input logic element also having an internal disable input; and

a protection circuit having an output coupled to the internal disable inputs of the logic modules and supplying a first voltage signal onto the internal disable inputs during a first power up period and supplying a second voltage signal onto the internal disable inputs during a second power up period, the second power up period starting before a supply voltage VCC of the field programmable gate array reaches steady state,

wherein the first voltage signal has a magnitude which increases as the supply voltage VCC increases and wherein the second voltage signal is ground potential.

12. A field programmable gate array, comprising:

an interconnect structure comprising routing conductors;

a plurality of logic modules, each of the logic modules having an input logic element, the input logic element having a plurality of inputs which when the field programmable gate array is unconfigured are not coupled to an output of any logic module, the input logic element also having an internal disable input; and

a protection circuit having an output coupled to the internal disable inputs of the logic modules and supplying a first voltage signal onto the internal disable inputs during a first power up period and supplying a second voltage signal onto the internal disable inputs during a second power up period, the second power up period starting before a supply voltage VCC of the field programmable gate array reaches steady state, wherein the interconnect structure comprises antifuses.

13. The field programmable gate array of claim 12, further comprising:

a charge pump having an output, wherein each logic module has outputs, each logic module output comprising a protection transistor having a gate, the gate of each protection transistor being coupled to the output of the charge pump.

14. The field programmable gate array of claim 13, wherein the protection transistors are made nonconductive during antifuse programming.

15. A field programmable gate array, comprising a plurality of logic cells, an interconnect structure, a charge pump, and a protection circuit, the protection circuit outputting a first voltage signal to each of the logic cells during a power up period until a voltage output by the charge pump reaches a predetermined voltage, the protection circuit outputting a second voltage signal to each of the logic cells after the voltage output by the charge pump reaches the predetermined voltage.

16. The field programmable gate array of claim 15, wherein the first voltage signal is substantially equal to a supply voltage supplied to the field programmable gate array, and wherein the second voltage signal is substantially equal to ground potential supplied to the field programmable gate array.