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Multi level power converter with self-correcting capacitor charge timing adjustment

  • US 5,828,561 A
  • Filed: 08/16/1996
  • Issued: 10/27/1998
  • Est. Priority Date: 12/29/1994
  • Status: Expired due to Term
First Claim
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1. A multilevel converter comprising, in particular, between a voltage source (SE) and a current source (C), a succession of controllable switching cells (CL1, CL2, . . . , CLn), each having two switches (T1, T'"'"'1;

  • T2, T'"'"'2;

    . . . ;

    Tn, T'"'"'n), with one pole of each of the two switches forming part of a pair of upstream poles and with the other pole of each of the switches forming one of a pair of downstream poles, the pair of downstream poles of an upstream cell being connected to the pair of upstream poles of a downstream cell, and the pair of upstream poles of a first cell (CL1) being connected to said current source (C) while the pair of downstream poles of a last cell (CLn) is connected to said voltage source (SE), the converter further comprising a capacitor (C1, C2, . . . , Cn) for each cell, except that the capacitor of the last cell may be omitted when said voltage source (SE) is suitable for performing the same role, each capacitor being connected between the two poles constituting the pair of downstream poles of the corresponding cell, the converter also comprising control means governing the nominal operation of the converter by acting on the switches of successive cells in such a manner that the two switches of any given cell are always in respective opposite conduction states, such that in response to a cell control signal (CT1, CT2, . . . , CTn) provided by said control means, one of the two switches in a given cell is successively in a first conduction state and then in a second conduction state during a cyclically repeated period, and such that in response to cell control signals that are identical but offset in time by a fraction of said period the switches of successive cells operate respectively in the same manner but offset in time by said fraction of a period, the successive capacitors (C1, C2, . . . , Cn) having respective increasing nominal mean charge voltages, the nominal mean charge voltage of the capacitor in each of said cells being equal to the product of a voltage (VE) from said voltage source (SE) multiplied by the reciprocal of the number of cells and by the rank of the cell, the converter being characterized in that it comprises means (VMO1, VMO2, . . . , VMOn) for evaluating the mean voltage across the terminals of each capacitor (C1, C2, . . . , Cn), means (VE1, VE2, . . . , VEn) for measuring any difference on each of said capacitors (C1, C2, . . . , Cn) between the evaluated mean charge voltage and the nominal mean charge voltage of the capacitor, and for delivering corresponding difference signals (VEC1, VEC2, . . . , VECn), and correction controlling means (BT, EC1, EC2, . . . , ECn) receiving said difference signals and consequently controlling at least one temporary coupling between two capacitors in order to correct said difference.

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