Integrated network switch having mixed mode switching with selectable full frame/half frame switching

• US 5,828,664 A
• Filed: 02/18/1997
• Issued: 10/27/1998
• Est. Priority Date: 06/10/1994
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Weir, Steven
• Primary Examiner(s): TON, DANG T
• Application Number:
  US08/802,436
• Time in Patent Office: 616 Days
• Field of Search: 370/363, 370/468, 370/575, 370/360, 370/460, 370/376, 370/428, 370/355, 370/375, 370/524, 370/522, 370/523, 370/503, 370/350, 370/362, 370/412, 370/377, 370/378, 370/379, 370/381, 370/382, 370/384, 340/825.01, 340/825.02, 340/825.03, 340/825.5, 340/825.51, 374/202, 374/229, 374/237, 374/240, 375/242, 375/222, 375/225, 375/211, 395/821, 395/823, 395/827, 395/828, 395/831, 395/833, 395/834, 395/840, 395/850, 395/851, 395/853, 395/864
• US Class Current: 370/375
• CPC Class Codes: H04Q 11/0407 using a stored programme control
• CPC Class Codes: H04Q 11/0414 Details
• CPC Class Codes: H04Q 2213/13003 Constructional details of switching devices
• CPC Class Codes: H04Q 2213/1302 Relay switches
• CPC Class Codes: H04Q 2213/13034 A/D conversion, code compression/expansion
• CPC Class Codes: H04Q 2213/1304 Coordinate switches, crossbar, 4/2 with relays, coupling field
• CPC Class Codes: H04Q 2213/1308 Power supply
• CPC Class Codes: H04Q 2213/13103 Memory
• CPC Class Codes: H04Q 2213/13106 Microprocessor, CPU
• CPC Class Codes: H04Q 2213/13213 Counting, timing circuits
• CPC Class Codes: H04Q 2213/13292 Time division multiplexing, TDM
• CPC Class Codes: H04Q 2213/13299 Bus
• CPC Class Codes: H04Q 2213/1332 Logic circuits
• CPC Class Codes: H04Q 2213/13322 Integrated circuits
• CPC Class Codes: H04Q 2213/13405 Dual frequency signaling, DTMF

Abstract

An integrated network switch operable in either full-frame or half-frame switching modes on a circuit-by-circuit basis. To effect selective operation in either full-frame or half-frame switching modes, an information memory buffer has the capacity of storing two samples per port. A connection memory contains the source addresses for the output ports. The most significant bit of an address designates the first or second sample of the two sample information memory buffer. For half-frame mode operation, the current value of the most significant bit of the write pointer (the address being written to) is used in the source address for reading when the source address is less than the write pointer. However, when the source address is greater than the write pointer, the most significant bit position is switched. For full-frame mode operation, the most significant bit of the source address will always take the inverse of the most significant bit for the write pointer. This assures that the read frame is always in the half of the two sample buffer not then being written to.

Claims

1. An integrated network switch for establishing communication paths among a plurality of peripherals, comprising:

a multi-frame information memory for storing multi-frame information in at least first and second memory cells at memory locations corresponding to source ports;

a connection memory storing for each destination port an information memory source port address;

means for operating the integrated network switch in a half-frame operating mode;

means for operating the integrated network switch in a full-frame operating mode; and

means for detecting connection of each of said peripherals to the integrated network switch and selectively enabling the half-frame operating mode means and the full-frame operating mode means depending on the peripheral connected to the integrated network switch.

2. For an integrated network switch including a multi-frame information memory for storing multi-frame information in at least first and second memory cells at memory locations corresponding to source ports and a connection memory storing for each destination port an information memory source port address, the integrated network switch performing connections among a plurality of peripherals, a method for retrieving information data from said information memory comprising:

detecting which peripheral of the plurality of peripherals is connected to said integrated network switch;

providing an indicator as part of the data received from the source port to enable a half-frame operating mode or a full-frame operating mode of said integrated network switch depending on the peripheral detected to be connected to said integrated network switch; and

selectively operating the integrated network switch in the half-frame operating mode or the full-frame operating mode depending on said indicator.