Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface

• US 5,828,854 A
• Filed: 09/26/1996
• Issued: 10/27/1998
• Est. Priority Date: 01/27/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wade, Nicholas D.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): Lefkowitz, Sumati
• Application Number:
  US08/721,271
• Time in Patent Office: 761 Days
• Field of Search: 395/306-309, 395/311-312, 395/857-858
• US Class Current: 710/315
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/405 where the bridge performs a synchronising function

Abstract

An apparatus and method for connecting a bus bridge to a plurality of bus interfaces are disclosed. The invention allows output lines on a bus bridge to be shared so that a minimal amount of dedicated pins are utilized. Signals on the bus bridge which need to be driven and received quickly are connected directly from the bus bridge to the bus interfaces. Signals on the bus bridge which do not need to be driven and received quickly are connected from the bus bridge to the bus interfaces though buffers. The invention allows the bus bridge to interface a high speed local bus and a plurality of I/O buses while satisfying the timing requirements of each of the I/O buses.

Claims

1. An apparatus, comprising:

a first plurality of pins that transmit first bus signals with tight timing requirements to a first bus and that transmit second bus signals with timing requirements that are not tight to a second bus; and

a second plurality of pins that transmit second bus signals with tight timing requirements to the second bus and that transmit first bus signals with timing requirements that are not tight to the first bus.

2. The apparatus of claim 1, wherein the first bus is an ISA bus and the second bus is an ATA bus.

3. The apparatus of claim 1, wherein the first bus signals with tight timing requirements are latched address signals.

4. The apparatus of claim 1, wherein the second bus signals with tight timing requirements are disk data signals.

5. The apparatus of claim 1, wherein the second bus signals with timing requirements that are not tight are disk address signals.

6. The apparatus of claim 1, wherein the second bus signals with timing requirements that are not tight are chip select signals.

7. The apparatus of claim 1, wherein the first bus signals with timing requirements that are not tight are system address signals.

8. The apparatus of claim 1, wherein the first bus signals with timing requirements that are not tight are system byte high enable signals.

9. An apparatus, comprising:

direct connections, from the apparatus to a first bus and a second bus, that transmit signals with tight timing requirements; and

buffered connections, from the direct connections, that transmit signals with timing requirements that are not tight.

10. The apparatus of claim 9, wherein the first bus is an ISA bus and the second bus is an ATA bus.

11. The apparatus of claim 9, wherein the signals with tight timing requirements are latched address signals and disk data signals.

12. The apparatus of claim 9, wherein the signals with timing requirements that are not tight are disk address signals.

13. The apparatus of claim 9, wherein the signals with timing requirements that are not tight are chip select signals.

14. The apparatus of claim 9, wherein the signals with timing requirements that are not tight are system address signals.

15. The apparatus of claim 9, wherein the signals with timing requirements that are not tight are byte high enable signals.

16. A bus bridge transmitting signals to an ISA bus and an ATA bus, comprising:

a first direct connection, from the bus bridge to the ISA bus, that transmits latched address signals;

a second direct connection, from the bus bridge to the ATA bus, that transmits disk data signals, disk address signals, and chip select signals;

a first buffered connection, from the second direct connection, that transmits system address and system byte high enable signals.

17. A bus bridge transmitting signals to an ISA bus and an ATA bus, comprising:

a first direct connection, from the bus bridge to the ISA bus, that transmit latched address signals, system address signals, and system byte high enable signals;

a second direct connection, from the bus bridge to the ATA bus, that transmits disk data signals; and

a first buffered connection, from the first direct connection to the ATA interface, that transmits disk address and chip select signals.

18. A method for transmitting signals to a first bus and a second bus, comprising:

transmitting signals with tight timing requirements on direct connections from a bus bridge to the first bus and the second bus;

transmitting signals with timing requirements that are not tight on buffered connections from the direct connections.

19. The method of claim 18, wherein the first bus is an ISA bus and the second bus is an ATA bus.

20. The method of claim 18, wherein the signals with tight timing requirements are latched address signals and disk data signals.

21. The method of claim 18, wherein the signals with timing requirements that are not tight are disk address signals.

22. The method of claim 18, wherein the signals with timing requirements that are not tight are chip select signals.

23. The method of claim 18, wherein the signals with timing requirements that are not tight are system address signals.

24. The method of claim 18, wherein the signals with timing requirements that are not tight are system byte high enable signals.