Pipeline system and method for multiprocessor applications in which each of a plurality of threads execute all steps of a process characterized by normal and parallel steps on a respective datum

• US 5,828,880 A
• Filed: 07/06/1995
• Issued: 10/27/1998
• Est. Priority Date: 07/06/1995
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Hanko, James G.
• Primary Examiner(s): BANANKHAH, MAJID A
• Application Number:
  US08/499,287
• Time in Patent Office: 1,209 Days
• Field of Search: 395/672, 395/673, 395/375, 395/676, 395/390, 395/670, 395/800.16, 395/800.13
• US Class Current: 718/106
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A pipelined process execution control system for multiprocessors is disclosed that enables multiple processors to cooperatively execute one or many software processes so that cache locality is not violated and extensive state, or context, information need not be saved and restored for each small piece of work performed on multiple data items. The present pipelined process execution control system incorporates (1) a software procedure defined as a pipelined sequence of normal or parallel steps, (2) multiple threads running on the multiprocessor, each of which executes the entire sequence of steps on one datum or data item from a received data stream, and (3) a process control structure to control the threads executing the sequence of steps, so that the normal steps are executed by only one thread at a time and the threads begin executing (or "enter") subsequent normal steps in the sequence in the same order as the threads entered the first step of the sequence. Parallel steps can be executed by more than one thread in parallel. The process control structure provides a process control data structure to track which of the steps is currently being executed by each thread. To eliminate the possibility of simultaneous memory access attempts by the multiple processors hosting the threads, the process control data structure is accessible to only one thread at a time. One specific process control structure disclosed is a mutex combined with a mutex control data structure.

Claims

1. A pipeline method for executing a process on a multiprocessor computer system having a plurality of processors and a memory, wherein said process includes a plurality of steps, each of said steps being classified as a normal step or a parallel step, said method comprising the steps of:

receiving a data stream including a plurality of datums;

executing a plurality of threads on said plurality of processors, each of said threads executing all of said plurality of steps on a respective one of said datums;

said executing step including executing each of said normal steps by at most one of said threads at a time;

said executing step further including executing each of said parallel steps by any number of said threads at a time;

said executing step including constraining said threads to execute said normal steps in the same order that said threads begin execution of said process on successively received ones of said datums.

2. The pipeline method of claim 1, wherein each of said steps is classified as said normal step or said parallel step by a classifier that analyzes said procedure.

3. The pipeline method of claim 1, wherein each of said steps is classified as said normal step or said parallel step based on classification data stored in said memory, said classification data being indexed to said steps of said procedure.

4. The pipeline method of claim 1, wherein said executing step is controlled by a process controller, said process controller comprising a process control data structure in said memory to track which of said steps is currently being executed by each of said threads, said process control data structure being accessible to only one of said threads at a time;

such that on completing a said step, a first thread with a first priority and access to said data structure begins executing a next normal step only upon verifying from said process control data structure that a second thread with a second priority immediately higher than said first priority has completed said next normal step.

5. The pipeline method of claim 4, wherein said process controller further comprises a mutex in said memory accessible to all of said threads but obtainable by only one of said threads at a time according to a cooperative scheme that ensures that each of said threads will eventually obtain said mutex, wherein said threads may read to or write from said data structure only after obtaining said mutex.

6. The pipeline method of claim 5, wherein said process control data structure further comprises a process list in said memory including a list header that addresses a linked list of thread status records, each of said thread status records uniquely representing thread status of a respective one of said threads running said sequence of steps, including which of said steps is currently being executed by said corresponding thread, said process list having a process list structure representing relative priorities of said threads.

7. The pipeline method of claim 6, wherein said process control data structure further comprises a thread status data structure in said memory of ordered thread status records, each of said thread status records uniquely representing thread status of one of said threads running said sequence of steps, including which of said steps is currently being executed by said corresponding thread.

8. The pipeline method of claim 1, wherein there is a one-to-one correspondence between said threads and said processors on which said threads are executing.

9. The pipeline method of claim 1, wherein some of said threads are executing on more than one of said processors.

10. In a microprocessor having a plurality of processors and a memory, a pipelined, process execution control system that controls execution of a procedure having a sequence of steps for processing a received data stream having a plurality of datums, each of said steps being classified as one of a normal step or a parallel step, said process execution control system comprising:

a thread loader that loads said plurality of processors with a plurality of threads, each of said threads executing all of said steps of said procedure on a respective one of said datums; and

a thread controller that coordinates said threads executing said procedure so that said threads execute said normal steps in the same order that said threads execute the first step of said sequence of steps and no more than one of said threads executes one of said single steps at a time.

11. The pipelined process execution control system of claim 10, further comprising:

a classifier for classifying each of said steps as one of said normal step or said parallel step.

12. The pipelined process execution control system of claim 10, further comprising:

classification data stored in said memory for classifying each of said steps as one of said normal step or said parallel step, said classification data being indexed to said steps of said procedure.

13. The pipelined, process execution control system of claim 10, wherein said thread controller comprises a process control data structure to track which of said steps is currently being executed by each of said threads, said process control data structure being accessible to only one of said threads at a time;

wherein, on completing a said step, a first thread with a first priority and access to said data structure begins executing a next normal step only upon verifying from said process control data structure that a second thread with a second priority immediately higher than said first priority has completed said next normal step.

14. The pipelined, process execution control system of claim 13, wherein said process controller further comprises a mutex in said memory accessible to all of said threads but obtainable by only one of said threads at a time according to a cooperative scheme that ensures that each of said threads will eventually obtain said mutex, wherein said threads may read to or write from said data structure only after obtaining said mutex.

15. The pipelined, process execution control system of claim 14, wherein said process control data structure further comprises a process list in said memory including a list header that addresses a linked list of thread status records, each of said thread status records uniquely representing thread status of one of said threads running said sequence of steps, including which of said steps is currently being executed by said corresponding thread, said process list having a process list structure representing relative priorities of said threads.

16. The pipelined, process execution control system of claim 15, wherein said process control data structure further comprises a thread status data structure of ordered thread status records, each of said thread status records uniquely representing thread status of one of said threads running said sequence of steps, including which of said steps is currently being executed by said corresponding thread.

17. The pipelined, process execution control system of claim 10, wherein said process controller allocates said threads among said processors.

18. The pipelined, process execution control system of claim 17, wherein said process controller allocates each of said threads to one of said processors.

19. The pipelined, process execution control system of claim 18, wherein said process controller allocates some of said threads to more than one of said processors.

20. A computer-readable memory that can be used to direct a microprocessor having a plurality of processors to control execution of a procedure having a sequence of steps for processing a received data stream having a plurality of datums, each of said steps being classified as one of a normal step or a parallel step, said computer-readable memory comprising:

a thread loader that loads said plurality of processors with a plurality of threads, each of said threads executing all of said steps of said procedure on a respective one of said datums; and

a thread controller that coordinates said threads executing said procedure so that said threads execute said normal steps in the same order that said threads execute the first step of said sequence of steps and no more than one of said threads executes one of said single steps at a time.

21. The computer-readable memory of claim 20, further comprising:

a classifier for classifying each of said steps as one of said normal step or said parallel step.

22. The computer-readable memory of claim 20, further comprising:

classification data stored in said memory for classifying each of said steps as one of said normal step or said parallel step, said classification data being indexed to said steps of said procedure.

23. The computer-readable memory of claim 20, wherein said thread controller comprises a process control data structure to track which of said steps is currently being executed by each of said threads, said process control data structure being accessible to only one of said threads at a time;

wherein, on completing a said step, a first thread with a first priority and access to said data structure begins executing a next normal step only upon verifying from said process control data structure that a second thread with a second priority immediately higher than said first priority has completed said next normal step.

24. The computer-readable memory of claim 23, wherein said process controller further comprises a mutex in said memory accessible to all of said threads but obtainable by only one of said threads at a time according to a cooperative scheme that ensures that each of said threads will eventually obtain said mutex, wherein said threads may read to or write from said data structure only after obtaining said mutex.

25. The computer-readable memory of claim 24, wherein said process control data structure further comprises a process list in said memory including a list header that addresses a linked list of thread status records, each of said thread status records uniquely representing thread status of one of said threads running said sequence of steps, including which of said steps is currently being executed by said corresponding thread, said process list having a process list structure representing relative priorities of said threads.

26. The computer-readable memory of claim 25, wherein said process control data structure further comprises a thread status data structure of ordered thread status records, each of said thread status records uniquely representing thread status of one of said threads running said sequence of steps, including which of said steps is currently being executed by said corresponding thread.

27. The computer-readable memory of claim 20, wherein said process controller allocates said threads among said processors.

28. The computer-readable memory of claim 27, wherein said process controller allocates each of said threads to one of said processors.

29. The computer-readable memory of claim 28, wherein said process controller allocates some of said threads to more than one of said processors.