Snooper circuit of a multi-processor system

• US 5,829,040 A
• Filed: 04/18/1997
• Issued: 10/27/1998
• Est. Priority Date: 04/11/1994
• Status: Expired due to Term

• Current Assignee: Jingpin Technologies, LLC (Intellectual Ventures LLC)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Min-hee
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): KING, CONLEY BURRELL
• Application Number:
  US08/839,346
• Time in Patent Office: 557 Days
• Field of Search: 395/468, 395/470, 395/472, 395/473, 711/141, 711/143, 711/145, 711/146
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means

Abstract

A snooper circuit of a multi-processor system includes a plurality of processor boards each having a central processing unit, a cache memory, a cache controller to control the cache memory and a snooper controller, a main memory, and a system bus for interconnecting these. The snooper circuit comprises an address tag memory, a state tag memory, a first comparator, a second comparator and the snooper controller for judging the address match between the other requester and the snooper controller by receiving the output of the first comparator, judging whether bus operation for the same address is doubly requested before the bus operation is finished by receiving the output of the second comparator, offering output predetermined cache coherency signal on the system bus according to the judged result and the address match signal between the other requester and the cache memory, and offering output first control signal for write-back, second control signal for updating state, third control signal for controlling a data buffer and fourth control signal for retrying of the CPU and referring or updating the data of the state tag memory, and maintains the cache coherency between the main memory and the cache memories.

Claims

1. A snooper circuit for maintaining cache coherency between the main memory and the cache memory in a multi-processor system including a plurality of processor boards each having a CPU, cache memory and cache controller for controlling the cache memory, which are connected to each other with a local bus, at least one main memory, and a system bus connecting the processor board and the main memory, the snooper circuit comprising:

an address tag memory for storing the address of the cache memory of the processor board to which the address tag memory belongs, receiving the address operated on the system bus by an other requester, and outputting an address match signal if the received address matches the stored address;

a state tag memory for storing the data state of the matched address;

a multiplexer for providing tag addresses to both said address tag memory and said state tag memory;

a first comparator for comparing the address driven by the other requester and the address driven by a snooper controller and generating an output indicative of the results of the comparison;

a second comparator for latching the address driven by the CPU at the starting time of the CPU'"'"'s bus operation, and comparing the monitored address on the system bus with the latched address at a predetermined interval and generating an output indicative of the results of the comparison; and

the snooper controller for receiving the output of the first comparator, determining, before finish of the bus operation requested by a specific requester, whether the other requester requests the bus operation for the same address according to the output of the second comparator, outputting a predetermined cache coherency signal on the system bus according to the determined results and the address match signal, outputting on-the local bus a first control signal for write-back, a second control signal for updating state, a third control signal for controlling a data buffer and fourth control signal for retrying of the CPU, and referring or updating the state tag memory.

2. The multi-processor system as claimed in claim 1, wherein the snooper controller outputs a SHARED signal indicating that cache data is commonly stored in the plurality of processor boards, a DIRTY signal indicating that the data of the main memory is not consistent with the data of the cache memory and a SNACK signal for notifying that the current operation of the system bus cannot be executed to the snooper controller of other processor boards.

3. The multi-processor system as claimed in claim 1, wherein the state tag memory uses SHARED, DIRTY, VALID and INVALID data states.

4. A multi-processor system comprising:

a plurality of processor boards each having a CPU, cache memory and cache controller for controlling the cache memory, which are connected to each other with a local bus;

at least one main memory;

a system bus connecting the processor board and the main memory; and

a snooper circuit located on the processor board, the snooper circuit including;

address tag memory means for storing an address of the cache memory of the processor board to which the address tag memory belongs, receiving the address operated on the system bus by an other requester, and outputting an address match signal if the received address matches the stored address;

a state tag memory for storing data state of the matched address;

a multiplexer for providing tag addresses to both said address tag memory and said state tag memory;

a first comparator means for comparing the address driven by the other requester and the address driven by snooper controller and generating a signal indicative of the results of the comparison;

a second comparator means for latching the address driven by the CPU at the starting time of the CPU'"'"'s bus operation, and comparing the monitored address on the system bus with the latched address at a predetermined interval and generating a signal indicative of the results of the comparison; and

a snooper controller means for determining whether the address driven by the other requester matches the address of the snooper controller according to the signal of the first comparator, determining, before finish of the bus operation requested by a specific requester, whether the other requester requests the bus operation for the same address according to the signal of the second comparator, outputting a predetermined cache coherency signal on the system bus according to the determined results and the address match signal, outputting on the local bus a first control signal for write-back, a second control signal for updating state, a third control signal for controlling a data buffer and fourth control signal for retrying of the CPU, and