Devices and systems with parallel logic unit operable on data memory locations
First Claim
1. A data processing device, comprising:
- a central processing unit (CPU) having memory mapped access to predetermined registers and capable of generating direct addresses; and
,an address generator directly associated with said CPU including said predetermined registers and capable of operating in parallel with said CPU to generate indirect addresses without using said CPU and;
wherein said CPU accesses registers that are in the address generator of the CPU without adding a register address field to an instructor.
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Abstract
A data processing device includes a first memory for storing data, a second memory for storing instructions and circuitry connected to the first memory for electronically performing computation operations. Registers temporarily hold digital signals representative of first values on which computations are based and second values that are computed. Address decoding circuitry has an input connected to an address bus. The address decoding circuitry has outputs connected to the registers to decode addresses from the address bus and access the registers. A control circuit is connected to the second memory and responds to at least one of the instructions for sending an address via the address bus to the address decoding circuitry to transfer a value in a first one of the registers directly to a second one of the registers thereby bypassing the first memory during the transfer. Other devices, systems and methods are also disclosed.
30 Citations
55 Claims
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1. A data processing device, comprising:
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a central processing unit (CPU) having memory mapped access to predetermined registers and capable of generating direct addresses; and
,an address generator directly associated with said CPU including said predetermined registers and capable of operating in parallel with said CPU to generate indirect addresses without using said CPU and; wherein said CPU accesses registers that are in the address generator of the CPU without adding a register address field to an instructor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A data processing device, including:
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a central processor; a data memory; a program bus; a data bus; and
,address circuitry including memory mapped registers for generating direct data addresses from said data or program bus, for generating indirect data addresses using one or more of said registers, and for using immediate operands for addresses, and for requesting delivery of data in said data memory identified by said data addresses to said central processor; and wherein said central processor communicates with said data memory and address circuitry through said data bus and accesses registers associated with the address circuitry without adding a register address field to an instruction. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
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54. A data processing device, including:
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a central processor unit (CPU); a data memory; a program bus; a data bus; a data address bus; direct address circuitry including a data memory page pointer for generating direct addresses and sending said direct addresses to said data address bus; selector circuitry controlled by said CPU for selectively filling said page pointer with a page address; a data memory word pointer being filled with a word address from said program bus and being concatenated with said page pointer to create a data memory address used for accessing said data memory; address circuitry for generating indirect addresses and including an address generator and a series of auxiliary registers for providing a data memory address for accessing said data memory; wherein said address generator sends said data memory address to said data address bus, has circuitry for manipulating the contents of a selected register, and includes a register pointer for selecting one of said registers; and immediate address circuitry for immediately manipulating data or addresses without referencing a data address; and wherein said auxiliary registers are memory mapped for addressing by said central processor unit and said indirect address circuitry and said central processor unit accesses registers of said address generator without adding a register field to an instruction.
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55. A method for addressing data in a data processing device, having:
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a central processor with at least one register, an address generator with auxiliary registers, a data memory, and, circuitry for communicating between said central processor, address generator, and data memory; said method for addressing, a) memory mapping said auxiliary registers; b) accessing and manipulating the contents of said auxiliary registers by said central processor using a memory address;
said contents comprising data addresses;c) requesting release of data from data memory stored in accessible location corresponding to said data addresses, and, d) sending said data to said central processor for access and manipulation, whereby said central processor accesses registers associated with the addresses generator without adding a register field to an instruction.
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Specification