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Devices and systems with parallel logic unit operable on data memory locations

  • US 5,829,054 A
  • Filed: 02/26/1997
  • Issued: 10/27/1998
  • Est. Priority Date: 05/04/1989
  • Status: Expired due to Fees
First Claim
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1. A data processing device, comprising:

  • a central processing unit (CPU) having memory mapped access to predetermined registers and capable of generating direct addresses; and

    ,an address generator directly associated with said CPU including said predetermined registers and capable of operating in parallel with said CPU to generate indirect addresses without using said CPU and;

    wherein said CPU accesses registers that are in the address generator of the CPU without adding a register address field to an instructor.

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