Direct multilevel thin-film transistors production method

• US 5,830,785 A
• Filed: 02/22/1996
• Issued: 11/03/1998
• Est. Priority Date: 03/16/1993
• Status: Expired due to Term

• Current Assignee: Kinetics Technology International Corp (TechnipFMC, plc)
• Original Assignee: Thomson Lcd
• Inventors: Hepp, Bernard, Sanson, Eric, Szydlo, Nicolas
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/522,243
• Time in Patent Office: 985 Days
• Field of Search: 437/40, 437/41, 437/51, 438/158, 438/30
• US Class Current: 438/158
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate

Abstract

The present invention can be used to make integrated circuits on the same substrate as the active matrix owing to the possibility that it offers of connecting transistor gates to sources or drains of the same or other transistors, and thus be used in a "integrated drivers" technology. It is also possible to make different types of transistors and capacitances using this method, without adding any additional mask levels.

Claims

1. A method for making direct multilevel thin-film transistors with three mask levels, comprising the steps of:

depositing and etching a first conducting level on an insulating substrate to form a source and a drain,

depositing during the same step a semiconductor level followed by an insulator level and etching of the assembly joining source and drain,

oxidizing, nitriding or passivating of edges of the semiconductor level, and

depositing and etching a conducting level to form the transistor gate.

2. A method according to claim 1 wherein sources, drains and gates are etched to form columns, pixel electrodes and rows respectively, for an active matrix liquid crystal screen.

3. A method according to claim 1, wherein the transistors comprise integral electronic control circuitry and/or signal processing electronics.

4. A method according to claim 1, wherein the insulated substrate is transparent.

5. A method according to claim 1, wherein the first conducting level is transparent.

6. A method according to claim 1, wherein the first transparent conducting level is doped on the surface.

7. A method according to claim 1, wherein the first conducting level is a double doped semiconductor layer.

8. A method according to claim 1, wherein a conducting level is directly deposited on the insulating substrate followed by a deposit of an insulating layer, forming the electrode and dielectric of a storage capacitance.

9. A method according to claim 1, wherein the substrate (10) is a glass plate.

10. A method according to claim 1, wherein the first transparent conducting level is composed of indium and tin oxide, or tin oxide.

11. A method according to claim 1, wherein the semiconductor materials are made of hydrogenated amorphous silicon, polycrystalline, or microcrystalline silicon.

12. A method according to claim 1, wherein the insulating materials are made of silicon dioxide, silicon nitride, or oxynitride.

13. A method according to claim 1, wherein conducting materials are made of aluminum, titanium, chromium, molybdenum, tungsten, tantalum, indium and tin oxide, alloys or multilayers.