Device and method for programming a logic level within an integrated circuit using multiple mask layers

• US 5,831,280 A
• Filed: 11/24/1997
• Issued: 11/03/1998
• Est. Priority Date: 09/23/1994
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ray, S. Doug
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US08/977,213
• Time in Patent Office: 344 Days
• Field of Search: 257/48, 257/209, 257/435, 430/313, 430/314, 438/942, 438/947
• US Class Current: 257/48
• CPC Class Codes: G03F 7/70541 Tagging, i.e. hardware or software tagging of features or components, e.g. using tagging scripts or tagging identifier codes for identification of chips, shots or wafers
• CPC Class Codes: H01L 27/02 including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: Y10S 438/942 Masking
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing

Abstract

A device and method is provided for programming an output logic level based on one or more revisions to mask layers utilized for forming an integrated circuit. The programmed logic level is represented as a logic value and is output from a device embodied within the integrated circuit formed from the mask layers. Each revision of mask layers is represented as a binary value at bit locations within a revision code output from the present system. The device and method hereof is used to program the system in accordance with an infinite numbers of mask layers and revisions to those mask layers. The programmed output from the system is represented as a revision code of numerous bits output through a pin location extending from the outer surface of a package surrounding the integrated circuit. Ready access to the pin location allows an end user to access and determine a version of integrated circuit product embodied within a sealed package, without opening the package and destroying the enclosed product.

Claims

1. A method for determining a mask layer revision used to produce an integrated circuit, said method comprising the steps of:

providing a plurality of mask layers, each mask layer comprises opaque elements arranged in a pattern across said mask layer and a portion of said opaque elements on each mask layer are confined within a programmable cell;

lithography forming from the programmable cell of each said mask layer a programmable circuit at respective layers within an integrated circuit;

electrically connecting said programmable circuit at one layer to another programmable circuit at another layer to form a series-connected device;

forming a mask layer revision by reconfiguring opaque elements on one of said plurality of mask layers and one said programmable cell;

stimulating the input of said series-connected device and, based on reconfigured said opaque elements, producing a programmed logic level at the output of said series-connected device; and

reading a logic value of said programmed logic level corresponding to said mask layer revision.

2. The method as recited in claim 1, wherein said lithography forming step comprises exposing an integrated circuit to one of said plurality of mask layers containing one said programmable cell and thereafter exposing said integrated circuit to other of said plurality of mask layers containing respective other said programmable cells.

3. The method as recited in claim 1, wherein said electrically connecting step comprises lithography forming a conductor during the step of lithography forming of said programmable circuit.

4. The method as recited in claim 1, wherein said stimulating step comprises applying a voltage magnitude at a fixed logic value.

5. The method as recited in claim 1, wherein said reading step comprises outputing said logic value of said programmed logic level stored within a register embodied upon said integrated circuit.