Self-shielding inductor for multi-layer semiconductor integrated circuits

• US 5,831,331 A
• Filed: 11/22/1996
• Issued: 11/03/1998
• Est. Priority Date: 11/22/1996
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Lee, Sheng-Hann
• Primary Examiner(s): OSTROWSKI, DAVID M
• Application Number:
  US08/754,346
• Time in Patent Office: 711 Days
• Field of Search: 257/277, 257/531, 257/659, 257/664, 257/665, 257/532
• US Class Current: 257/659
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An inductive structure for an integrated circuit. The inductor has a first turn that shields the other turns of the inductor from a proximate ground plane. Multiple turns are disposed one above another in respective metalization layers of the integrated circuit. The turns are partial loops and are electrically coupled end-to-end with vias. Predetermined ones of the turns have additional portions in different layers. An additional portion of a turn is an electrically conductive strip deposited above the turn in a higher metalization layer and electrically coupled to the turn, thereby increasing the surface area of the turn and decreasing resistance of the turn. A buried n-type loop disposed below the first turn and below the surface of the substrate shields the first turn from the capacitive effects of the substrate.

Claims

1. A self-shielding inductor for a semiconductor integrated circuit, comprising:

a plurality of electrically insulating layers; and

an electrical conductor disposed in a plurality of electrically coupled turns, the turns disposed between the insulating layers of the semiconductor integrated circuit and including a first turn disposed between a first insulating layer and a second insulating layer, and others of the plurality of turns disposed between other ones of the insulating layers, the first turn being nearer a ground plane of the integrated circuit than the other turns.

2. The inductor of claim 1, further comprising a buried n-type layer disposed in a substrate of the integrated circuit between the first turn and the ground plane.

3. The inductor of claim 2, wherein the buried n-type layer has a shape that conforms to the first turn.

4. The inductor of claim 1, wherein the first turn has a width sufficient to shield the other turns.

5. A self-shielding inductor for a semiconductor integrated circuit, comprising:

a substrate having opposed first and second surfaces, the first surface disposed against a ground plane;

an electrical conductor disposed on the second surface of the substrate in a first turn, the first turn having a first end and a second end;

an first electrically insulating layer disposed on the second surface of the substrate and covering the first turn;

an electrical conductor disposed on the first insulating layer in a second turn and having a first end and a second end, the first end electrically coupled to the second end of the first turn;

an second electrically insulating layer disposed on the first insulating layer and covering the second turn; and

an electrical conductor disposed on the second insulating layer in a third turn, the third turn having a first end and a second end electrically coupled to the second end of the second turn.

6. The inductor of claim 5, further comprising a buried n-type layer disposed beneath the second surface of the substrate and below the first turn.

7. The inductor of claim 6, wherein the buried n-type layer has a shape that conforms to the first turn.

8. The inductor of claim 5, wherein the first turn has a width sufficient to shield the other turns.

9. A self-shielding inductor with resistance equalization for a semiconductor integrated circuit, comprising:

a plurality of electrically insulating layers;

an electrical conductor disposed in a plurality of electrically coupled turns, the turns disposed between the insulating layers of the semiconductor integrated circuit and including a first turn disposed between a first insulating layer and a second insulating layer, and others of the plurality of turns disposed between other ones of the insulating layers, the first turn being nearer a ground plane of the integrated circuit than the other turns; and

an electrical conductor disposed on the second insulating layer and electrically coupled to the first turn as a first additional layer of the first turn.

10. The inductor of claim 9, wherein the plurality of turns includes a second turn and a third turn, and the plurality of insulating layers includes a third insulating layer, the second turn electrically coupled to the first turn and disposed on the second insulating layer, the third insulating layer disposed on the second insulating layer and covering the second turn and the first additional layer of the first turn, and the third turn electrically coupled to the second turn and disposed on the third insulating layer, and further comprising:

an electrical conductor disposed on the third insulating layer and electrically coupled to the second turn as an additional layer of the second turn;

an electrical conductor disposed on the third insulating layer and electrically coupled to the first additional layer of the first turn as a second additional layer of the first turn.

11. The inductor of claim 10, further comprising a buried n-type layer disposed beneath the second surface of the substrate and below the first turn.

12. The inductor of claim 11, wherein the buried n-type layer has a shape that conforms to the first turn.

13. A self-shielding inductor with resistance equalization for a semiconductor integrated circuit, comprising:

a substrate having opposed first and second surfaces, the first surface disposed against a ground plane;

an electrical conductor disposed on the second surface of the substrate in a first turn, the first turn having a first end and a second end;

an first electrically insulating layer disposed on the second surface of the substrate and covering the first turn;

an electrical conductor disposed on the first insulating layer and electrically coupled to the second end of the first turn as a first additional layer of the first turn;

an electrical conductor disposed on the first insulating layer in a second turn and having a first end and a second end, the first end electrically coupled to the second end of the first turn;

an second electrically insulating layer disposed on the first insulating layer and covering the first additional layer of the first turn and the second turn; and

an electrical conductor disposed on the second insulating layer in a third turn, the third turn having a first end and a second end electrically coupled to the second end of the second turn.

14. The inductor of claim 13, further comprising an electrical conductor disposed on the second insulating layer and electrically coupled to the second end of the second turn as an additional layer of the second turn.

15. The inductor of claim 14, further comprising an electrical conductor disposed on the second insulating layer and electrically coupled to the first additional layer of the first turn as a second additional layer of the first turn.

16. The inductor of claim 13, further comprising a buried n-type layer disposed between the first turn and the ground plane.

17. The inductor of claim 16, wherein the buried n-type layer has a shape that conforms to the first turn.

18. A self-shielding inductor for a semiconductor integrated circuit, comprising:

a substrate having opposed first and second surfaces, the first surface disposed against a ground plane;

an electrical conductor disposed on the second surface of the substrate in a first turn, the first turn having a first end and a second end;

an first electrically insulating layer disposed on the second surface of the substrate and covering the first turn; and

an electrical conductor disposed in a first spiral on the first insulating layer and having a first end and a second end, the first end electrically coupled to the second end of the first turn.

19. The inductor of claim 18, further comprising:

an second electrically insulating layer disposed on the first insulating layer and covering the first spiral; and

an electrical conductor disposed in a second spiral on the second layer and having a first end and a second end electrically coupled to the second end of the first spiral.

20. The inductor of claim 18, further comprising a buried n-type layer disposed between the first turn and the ground plane.

21. The inductor of claim 20, wherein the buried n-type layer has a shape that conforms to the first turn.