Flexible parity generation circuit

• US 5,831,393 A
• Filed: 04/02/1997
• Issued: 11/03/1998
• Est. Priority Date: 03/12/1992
• Status: Expired due to Term

• Current Assignee: EMC Corporation (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Tang, Tin S., Hohenstein, Gerald Lee, Carmichael, Richard D., Brant, William A., Nielson, Michael E.
• Primary Examiner(s): PALYS, JOSEPH E
• Application Number:
  US08/832,050
• Time in Patent Office: 580 Days
• Field of Search: 395/182.04, 395/182.02, 395/182.07, 395/185.05, 395/183.05, 395/183.08, 371/40.11, 371/40.4, 371/40.15, 371/49.1, 371/49.2, 371/51.1, 711/114, 711/112
• US Class Current: 714/52
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 2211/1054 Parity-fast hardware, i.e. dedicated fast hardware for RAID systems with parity
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence

Abstract

A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.

Claims

1. A multi-channel redundancy block generation circuit for n logical data channels, comprising:

an input bus selectively couplable to each of said n logical data channels for receiving a plurality of related data blocks and at least one associated redundancy block;

a memory device partitioned into n data storage locations for said related data blocks and said at least one associated redundancy block for each of said n logical data channels;

a multi-input redundancy block generator coupled to said memory device for receiving selected ones of said data blocks and at least one associated redundancy block corresponding to each of said n logical data channels in a timewise interleaved manner and generating updated redundancy block information in response thereto;

a switching circuit coupled to said input bus and to said memory device for interleaving said related data blocks and said at least one associated redundancy block from a different one of said n logical data channels for input to said multi-input redundancy block generator; and

an output bus operatively coupled to an output of said multi-input redundancy block generator for receiving said updated redundancy block information and applying said updated redundancy block information to a corresponding one of said n logical data channels.

2. The multi-channel redundancy block generation circuit of claim 1 wherein said memory device comprises n first-in/first-out registers.

3. The multi-channel redundancy block generation circuit of claim 1 wherein said memory device comprises a randomly accessible memory device having n non-overlapping data storage locations.

4. The multi-channel redundancy block generation circuit of claim 1 wherein said switching circuit further selectively applies said related data blocks and said at least one associated redundancy block for a selected one of said n logical data channels to said memory device.

5. The multi-channel redundancy block generation circuit of claim 1 wherein outputs from a particular one of said n data storage locations in said memory device corresponding to said selected one of said n logical data channels are output to said multi-input redundancy block generator.

6. The multi-channel redundancy block generation circuit of claim 1 further comprising:

an addressing circuit coupled to an address input of said memory device for directing said plurality of related data blocks and said at least one associated redundancy block for each of said n logical data channels to a corresponding one of said n data storage locations.

7. The multi-channel redundancy block generation circuit of claim 6 wherein said addressing circuit further comprises:

a counter associated with each of said plurality of logical data channels for providing a count to said addressing circuit indicating a pointer to a portion of one of said n data storage locations corresponding to a selected one of said n logical data channels.

8. The multi-channel redundancy block generation circuit of claim 6 wherein said counter is programmable with a block size of said data blocks on each of said n logical data channels.

9. The multi-channel redundancy block generation circuit of claim 1 wherein said switching circuit is configured for randomly interleaving said related data blocks and said at least one associated redundancy block from a different one of said n logical data channels for input to said multi-input redundancy block generator.

10. The multi-channel redundancy block generation circuit of claim 1 wherein said multi-input redundancy block generator is a two input redundancy block generator.