×

Flexible parity generation circuit

  • US 5,831,393 A
  • Filed: 04/02/1997
  • Issued: 11/03/1998
  • Est. Priority Date: 03/12/1992
  • Status: Expired due to Term
First Claim
Patent Images

1. A multi-channel redundancy block generation circuit for n logical data channels, comprising:

  • an input bus selectively couplable to each of said n logical data channels for receiving a plurality of related data blocks and at least one associated redundancy block;

    a memory device partitioned into n data storage locations for said related data blocks and said at least one associated redundancy block for each of said n logical data channels;

    a multi-input redundancy block generator coupled to said memory device for receiving selected ones of said data blocks and at least one associated redundancy block corresponding to each of said n logical data channels in a timewise interleaved manner and generating updated redundancy block information in response thereto;

    a switching circuit coupled to said input bus and to said memory device for interleaving said related data blocks and said at least one associated redundancy block from a different one of said n logical data channels for input to said multi-input redundancy block generator; and

    an output bus operatively coupled to an output of said multi-input redundancy block generator for receiving said updated redundancy block information and applying said updated redundancy block information to a corresponding one of said n logical data channels.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×