Output circuit for use in a semiconductor integrated circuit
First Claim
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1. An output circuit comprising:
- a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential;
a first switch coupled between said back gate and said gate of said first MOS transistor, said first switch being ON/OFF controlled by a control signal;
a first node supplied with a first potential;
a second node supplied with a second potential lower than the first potential;
a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential applying circuit including a first end coupled to said second node and a second end;
a second switch coupled between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled based on an enable signal and a potential at one of said source and said drain of said first MOS transistor;
a third node supplied with a first reference potential; and
a third switch connected between said back gate of said first MOS transistor and said third node,wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch, thereby to operate said first MOS transistor in a sub-threshold region.
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Abstract
An output circuit comprising an output stage and a control signal generator. The output stage is constituted by a first P-channel MOS transistor and an N-channel MOS transistor. The control signal generator generates a signal for driving the gates of the MOS transistors, it comprises a NAND gate, a NOR gate NOR1 and an inverter INV1. The first P-channel MOS transistor of the output stage has a source and a back gate which are isolated in terms of potential. A second P-channel MOS transistor is provided, whose source-drain path is connected between the back gate and gate of the first P-channel MOS transistor incorporated in the output stage.
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Citations
36 Claims
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1. An output circuit comprising:
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a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential; a first switch coupled between said back gate and said gate of said first MOS transistor, said first switch being ON/OFF controlled by a control signal; a first node supplied with a first potential; a second node supplied with a second potential lower than the first potential; a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential applying circuit including a first end coupled to said second node and a second end; a second switch coupled between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled based on an enable signal and a potential at one of said source and said drain of said first MOS transistor; a third node supplied with a first reference potential; and a third switch connected between said back gate of said first MOS transistor and said third node, wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch, thereby to operate said first MOS transistor in a sub-threshold region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An output circuit comprising:
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a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential; a first switch coupled between said back gate and said gate of said first MOS transistor; a first node supplied with a first potential; a second node supplied with a second potential lower than the first potential; a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential-applying circuit including a first end coupled to said second node and a second end; a second switch coupled between said first node and said second end of said potential applying circuit, said second switch being ON/OFF controlled based on an enable signal and a potential at one of said source and said drain of said first MOS transistor; and a third switch coupled between said back gate and said source of said first MOS transistor, wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch, thereby to operate said first MOS transistor in a sub-threshold region. - View Dependent Claims (13, 14, 15, 16)
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17. An output circuit comprising:
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a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential; a first switch coupled between said back gate and said gate of said first MOS transistor; a first node supplied with a first potential; a second node supplied with a second potential lower than the first potential; a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential-applying circuit including a first end coupled to said second node and a second end; and a second switch coupled between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled based on an enable signal and a potential at one of said source and said drain of said first MOS transistor, wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch, thereby to operate said first MOS transistor in a sub-threshold region. - View Dependent Claims (18, 19, 20, 21)
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22. An output circuit comprising:
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a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential; a first node supplied with a first potential; a second node supplied with a second potential lower than the first potential; a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential-applying circuit having a node from which to apply the potential and including a first end coupled to said second node and a second end; a first switch coupled between said back gate of said first MOS transistor and said node of said potential-applying circuit; a second switch coupled between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled by an enable signal; a third node supplied with a first reference potential; and a third switch coupled between said back gate of said first MOS transistor and said third node, wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch and through said potential-applying circuit, thereby to operate said first MOS transistor in a sub-threshold region. - View Dependent Claims (23, 24)
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25. An output circuit comprising:
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a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential; a first node supplied with a first potential; a second node supplied with a second potential lower than the first potential; a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential-applying circuit having a node from which to apply the potential and including a first end coupled to said second n ode and a second end; a first switch coupled between said back gate of said first MOS transistor and said node of said potential-applying circuit; a second switch connected between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled by an enable signal; and a third switch connected between said back gate and said source of said first MOS transistor, wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch and through said potential-applying circuit, thereby to operate said first MOS transistor in a sub-threshold region. - View Dependent Claims (26, 27)
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28. An output circuit comprising:
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a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential; a first node supplied with a first potential; a second node supplied with a second potential lower than the first potential; a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential-applying circuit having a node from which to apply the potential and including a first end coupled to said second node and a second end; a first switch coupled between said back gate of said first MOS transistor and said node of said potential-applying circuit; and a second switch coupled between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled by an enable signal, wherein a potential is generated at said back gate of said first MOS transistor so that said source and said back gate of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate of said first MOS transistor, and the potential at said back gate is applied to said gate of said first MOS transistor through said first switch and through said potential-applying circuit, thereby to operate said first MOS transistor in a sub-threshold region. - View Dependent Claims (29, 30)
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31. An output circuit comprising:
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a first node supplied with a high potential; a second node supplied with a low potential; an output terminal; a first MOS transistor having a source coupled to said first node, a drain coupled to said output terminal, a gate, and a back gate isolated from said source in terms of potential; a potential-applying circuit for applying a potential; a first path gate coupled between said back gate and said gate of said first MOS transistor; a second path gate coupled between an output node of said potential-applying circuit and said gate of said first MOS transistor; a third path gate coupled between said output node of said potential-applying circuit and said gate of said first MOS transistor; and a control circuit supplied with the high potential and the low potential and a potential of said output terminal, for applying the potential of said output terminal or the low potential, which is required to render said second path gate conducting, to said second path gate in accordance with a control signal, for applying a potential, which is required to control the ON/OFF state of said first path gate, to said first path gate in accordance with the control signal, and for applying a potential, which is required to control the ON/OFF state of said third path gate, to said third path gate in accordance with the control signal, wherein a voltage is generated at said back gate of said first MOS transistor so that said back gate and said source of said first MOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate, and is applied from said back gate to said gate of said first MOS transistor through said first path gate, thereby to operate said first MOS transistor in a sub-threshold region.
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32. An output circuit comprising:
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a first node supplied with a high potential; a second node supplied with a low potential; an output terminal; a PMOS transistor having a source coupled to said first node, a drain coupled to said output terminal, a gate, and a back gate isolated from said source in terms of potential; a potential-applying circuit for applying a potential; a first path gate coupled between said back gate and said gate of said PMOS transistor; a second path gate coupled between an output node of said potential-applying circuit and said gate of said PMOS transistor; a third path gate coupled between said output node of said potential-applying circuit and said gate of said PMOS transistor; and a control circuit supplied with the high potential and the low potential and a potential of said output terminal, for applying the potential of said output terminal or the low potential, which is required to render said second path gate conducting, to said second path gate in accordance with a control signal, for applying a potential, which is required to control the ON/OFF state of said first path gate, to said first path gate in accordance with the control signal, and for applying a potential, which is required to control the ON/OFF state of said third path gate, to said third path gate in accordance with the control signal, wherein a voltage is generated at said back gate of said PMOS transistor so that said back gate and said source of said PMOS transistor have a voltage difference which is substantially equal to a junction voltage of a parasitic pn-junction diode formed between said source and said back gate, and is applied from said back gate to said gate of said PMOS transistor through said first path gate, thereby to operate said PMOS transistor in a sub-threshold region. - View Dependent Claims (33, 34, 35)
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36. An output circuit comprising:
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a first MOS transistor having a source, a drain, a gate and a back gate isolated from both said source and said drain in terms of potential; a first switch having a first terminal coupled to said back gate of first MOS transistor, a second terminal coupled to said gate of said first MOS transistor, and a control terminal supplied with a control signal for controlling the ON/OFF switching of said first switch; a first node supplied with a first potential; a second node supplied with a second potential lower than the first potential; a potential-applying circuit for applying a potential to said gate of said first MOS transistor, said potential-applying circuit including a first end coupled to said second node and a second end; and a second switch coupled between said first node and said second end of said potential-applying circuit, said second switch being ON/OFF controlled based on an enable signal and a potential at one of said source and said drain of said first MOS transistor.
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Specification