Graphics display system and method for providing internally timed time-varying properties of display attributes

• US 5,831,638 A
• Filed: 03/08/1996
• Issued: 11/03/1998
• Est. Priority Date: 03/08/1996
• Status: Expired due to Term

• Current Assignee: Lenovo PC International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Evans, Edward Kelley, West, Roderick Michael Peters
• Primary Examiner(s): Kim, Matthew M.
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/612,704
• Time in Patent Office: 970 Days
• Field of Search: 395/119, 395/120, 395/126, 395/132, 395/501-503, 395/507-510, 395/515, 348/42, 348/51, 348/55, 348/57, 348/58, 348/593-596, 345/114, 345/115, 345/185-190, 345/203, 345/501, 345/503, 345/507-510, 345/515, 345/186, 345/188
• US Class Current: 345/539
• CPC Class Codes: G09G 2310/0229 De-interlacing
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 3/003 to produce spatial visual effects
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/30 Control of display attribute
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A graphics display subsystem providing internally timed time-varying properties of display attributes is provided. The graphics display subsystem comprises a display device for displaying consecutive image frames of pixels having a variable display property, and a circuit for transferring image frames to the display device. One or more pixels are selected when a display attribute associated with the one or more pixels is set in an attribute table. The circuit varies, during a selected time interval, the display property of the selected pixels being displayed on the display device. In preferred embodiments, the variable display property is either a stereo image display, an image brightness control, or an image-blending control.

Claims

1. A graphics display subsystem having an internally timed stereo display, said graphics display subsystem comprising:

first and second buffer means for storing pixel data;

a display device for displaying consecutive image frames;

a memory for storing a plurality of attributes, said plurality of attributes including a stereo display enable attribute, a double buffer select attribute that defines the first buffer means as a right-eye buffer containing a right-eye image frame, and a double buffer enable attribute that enables and disables double buffer display and stereo display; and

a circuit for transferring image frames to the display device, said circuit including;

a signal generator for outputting a stereo select signal, the stereo select signal switching to a first polarity during a first frame blanking period of the display device and to a second polarity during an adjacent frame blanking period of the display device;

a first ANDgate having the stereo select signal and the stereo enable signal as inputs;

an XORgate having the output of the first ANDgate and the double buffer select signal as inputs; and

a second ANDgate having the output of the XORgate and the double buffer enable signal as inputs, the output of the second ANDgate indicating which of said first and second buffer means stores pixel data to be utilized for a current image frame;

wherein the circuit transfers pixel data from the first buffer means for display on the display device as a first image frame and transfers pixel data from the second buffer means for display on the display device as a second image frame, when the stereo display enable attribute within the graphics display subsystem is set.

2. A graphics display subsystem having an internally timed stereo display, said graphics display subsystem comprising:

a display device displaying image frames of pixels at a given frame rate, wherein each pixel of a given image frame belongs to a class of pixels;

a memory containing a plurality of attributes to be applied to a class of pixels, wherein the plurality of attributes includes a stereo display enable attribute indicating whether the class of pixels are to be displayed as a stereo display;

first and second buffer means for storing pixel data containing a first frame buffer and a second frame buffer, respectively;

a signal generator for outputting a stereo select signal, the stereo select signal switching to a first polarity during a first time interval and to a second polarity during an adjacent time interval; and

a buffer select circuit for generating a buffer select signal that selects one of the first frame buffer and the second frame buffer for a given pixel of a given image frame if the stereo display enable attribute indicates the given pixel is to be displayed as a stereo display, wherein the buffer select circuit receives the stereo select signal and generates a buffer select signal selecting the first frame buffer if receiving the first polarity of the received stereo select signal and selecting the second frame buffer if receiving the second polarity of the received stereo select signal, wherein a selected frame buffer for a given pixel is output to the display device to be displayed as the given pixel for the given image frame.

3. A graphics display subsystem having an internally timed stereo display according to claim 2, wherein the plurality of attributes includes a double buffer select attribute, which defines a buffer as the first buffer, and a double buffer enable attribute, which enables double buffer display and stereo display, and wherein the buffer select circuit is enabled by the double buffer attribute.

4. A graphics display subsystem having an internally timed stereo display according to claim 3, wherein the buffer select circuit comprises a first ANDgate having the stereo select signal and the stereo enable signal as inputs, a XORgate having the output of the first ANDgate and the double buffer select signal as inputs, and a second ANDgate having the output of the XORgate and the double buffer enable signal as inputs, the output of the second ANDgate being the buffer select signal.

5. A graphics display subsystem having an internally timed stereo display according to claim 2, wherein the display device has a frame blanking period between image frames and wherein the stereo select signal switches between polarities during frame blanking periods.

6. A method in a graphics display subsystem for providing an internally timed stereo display, the method comprising:

setting a plurality of attributes for one or more pixels of an image frame to be displayed as a stereo display, said plurality of attributes including a stereo display enable attribute, a double buffer select attribute that defines one of a first buffer and a second buffer as a right-eye buffer containing a right-eye image frame, and a double buffer enable attribute that enables double buffer display and stereo display;

generating a stereo select signal that switches between a first polarity and a second polarity during adjacent frame blanking periods of a display device;

generating a buffer select signal that selects one of the first frame buffer and the second frame buffer for a given pixel of a given image frame if the stereo display enable attribute indicates the given pixel is to be displayed as a stereo display, wherein the buffer select circuit receives the stereo select signal and generates a buffer select signal selecting the first frame buffer if receiving the first polarity of the received stereo select signal and selecting the second frame buffer if receiving the second polarity of the received stereo select signal; and

displaying, within the display device, pixel data from the buffer selected by the buffer select signal for every pixel of an image frame having a set stereo display enable attribute.

7. A method in a graphics display subsystem for providing an internally timed stereo display according to claim 6, wherein generating a buffer select signal includes switching the selection of a buffer during a frame blanking period of a display device displaying the image frame.