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Address strobe recognition in a memory device

  • US 5,831,931 A
  • Filed: 07/09/1997
  • Issued: 11/03/1998
  • Est. Priority Date: 11/06/1995
  • Status: Expired due to Term
First Claim
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1. A memory device comprising:

  • a plurality of column address strobe signals; and

    means for providing a signal based upon the plurality of column address strobe signals such that the signal transitions to a low logic state in response to one of the plurality of column address strobe signals which transitions to a low logic state first, and the signal transitions to a high logic state in response to one of the plurality of column address strobe signals which transitions to a high logic state first.

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