Self-enabling pulse-trapping circuit
First Claim
Patent Images
1. An integrated memory device comprising:
- a control signal input for receiving a control signal;
an address latch input for receiving an address latch signal; and
means for a latching a transition in the control signal when the address latch signal is activated.
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Abstract
An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. An external input is used to terminate and change a burst operation. Circuitry is provided to monitor the external input during burst operations and provide an appropriate control signal.
129 Citations
23 Claims
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1. An integrated memory device comprising:
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a control signal input for receiving a control signal; an address latch input for receiving an address latch signal; and means for a latching a transition in the control signal when the address latch signal is activated. - View Dependent Claims (2, 3)
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4. An integrated memory device comprising:
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a control signal input for receiving a control signal; an address latch input for receiving an address latch signal; and a signal trapping circuit coupled to the control signal input and the address latch input and adapted to latch a transition in the control signal, wherein the signal trapping circuit comprises; a high transition latch circuit to latch a low to high transition in the control signal when the address latch signal is activated, the high transition latch circuit comprises; a first flip-flop circuit having first and second inputs, and an output, the first input is coupled to the control signal input, a first logic gate having a first input connected to the output of the first flip-flop circuit, a second input connected to the address latch input, and an output; a second flip-flop circuit having a first input connected to the output of the first logic gate, a second input, and first and second outputs; a second logic gate having an output connected to the second input of the second flip-flop circuit, a first input connected to the output of the first logic gate, and a second input connected to the address latch input; a feedback circuit connected to first output of the second flip-flop circuit and the second input of the first flip-flop circuit; and an first output circuit connected to the first and second outputs of the second flip-flop circuit a low transition latch circuit to latch a high to low transition in the control signal when the address latch signal is activated, the low transition latch circuit comprises; a third flip-flop circuit having first and second inputs, and an output, the first input is coupled to the control signal input, a third logic gate having a first input connected to the output of the third flip-flop circuit, a second input connected to the address latch input, and an output; a fourth flip-flop circuit having a first input connected to the output of the third logic gate, a second input, and first and second outputs; a fourth logic gate having an output connected to the second input of the fourth flip-flop circuit, a first input connected to the output of the third logic gate, and a second input connected to the address latch input; a feedback circuit connected to the first output of the fourth flip-flop circuit and the second input of the third flip-flop circuit; and an second output circuit connected to the first and second outputs of the fourth flip-flop circuit. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of latching a control signal in a memory circuit having a control signal input and an address latch input, the method comprising the steps of:
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receiving an address latch signal on the address latch input; receiving a control signal on the control signal input; filtering the control signal to eliminate a control signal which has a duration that is shorter than a pre-determined time; enabling a latch circuit in response to an active transition of the address latch signal; and latching a transition of the control signal. - View Dependent Claims (18, 19, 20)
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21. A method of generating an burst control signal in a memory circuit having a control signal input and an address latch input, the method comprising the steps of:
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receiving a column address latch signal on the address latch input; receiving a write enable control signal on the control signal input; filtering the write enable control signal to eliminate a write enable control signal which has an active state duration that is shorter than a pre-determined time; filtering the write enable control signal to eliminate a write enable control signal which has an inactive state duration that is shorter than a pre-determined time; enabling a latch circuit in response to an active transition of the address latch signal; and latching a transition of the write enable control signal. - View Dependent Claims (22, 23)
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Specification