Memory testing apparatus

• US 5,831,989 A
• Filed: 09/18/1997
• Issued: 11/03/1998
• Est. Priority Date: 09/18/1996
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Fujisaki, Kenichi
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/933,246
• Time in Patent Office: 411 Days
• Field of Search: 371/21.6, 371/21.1, 371/21.2, 365/201, 395/183.18
• US Class Current: 714/723
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

There is provided a memory testing apparatus which can read out the information of failure memory cells of a tested memory from a failure analysis memory having the same memory capacity as that of a memory under test and can complete in a short time period the process for computing the classified total of the number of memory cell failures occurred. The memory area of the failure analysis memory is subdivided into a plurality of memory blocks, a flag memory having the same number of addresses as the number of the subdivided memory blocks is provided, and an address is assigned to each of the memory blocks. When a failure occurs in one of the memory blocks, a logical "1" indicating failure information is written at an address of the flag memory corresponding to that memory block. After the test is completed, the address of the flag memory where the logical "1" has been written is detected and the contents of the memory block corresponding to the detected address are read out to compute the classified total of the failure information.

Claims

1. A memory testing apparatus comprising:

a failure analysis memory having the same storage capacity as that of a memory under test, and being accessed by the same address signal as that which is applied to the memory under test, said failure analysis memory storing, each time a failure memory cell is detected from the memory under test, failure memory cell information written at the same address of said failure analysis memory as that of the memory under test in which that failure memory cell resides; and

a failure relief analyzer for accessing all of the addresses of said failure analysis memory to read out the stored failure memory cell information therefrom after completion of the test, and computing position information in which the failure memory cell or cells reside and the total number of the failure memory cells, thereby to determine whether the relief of the tested memory is possible or not on the basis of the position information and the total number of the failure memory cells,

said memory testing apparatus being characterized by;

means for subdividing said failure analysis memory into a plurality of memory blocks;

a flag memory having its addresses corresponding to the subdivided memory blocks respectively, and storing at an address thereof corresponding to a memory block a flag representing that failure memory cell information has been written in that memory block;

address formatting means for taking out several bits from an address signal applied to said failure analysis memory, thereby to create an address signal for accessing all of the addresses of said flag memory, when testing a memory under test; and

computing means for accessing all of the addresses of said flag memory to read out the stored flag therefrom after completion of the test, and reading out only the stored contents of one or more memory blocks of said failure analysis memory corresponding to the address or addresses of the read-out one or more flags to compute position information of the failure memory cell or cells.

2. The memory testing apparatus according to claim 1, wherein said computing means comprises:

a row address generator for generating the same row address signal as a row address signal of an address signal applied to said failure analysis memory;

a column address generator for generating the same column address signal as a column address signal of the address signal applied to said failure analysis memory;

a flag address generator for generating a flag address signal for accessing all of the addresses of said flag memory after completion of the test;

second address formatting means for creating an address signal for accessing all of the addresses of one or more memory blocks corresponding to the address or addresses of one or more flags read out from said flag memory on the basis of the output signals from said flag address generator, said row address generator and said column address generator;

row failure cell storage means for storing therein the failure memory cell information relating to row addresses of failure memory cell information read out, after completion of the test, from one or more memory blocks in which failure memory cell information has been written;

column failure cell storage means for storing therein the failure memory cell information relating to column addresses of the failure memory cell information read out, after completion of the test, from said one or more memory blocks in which failure memory cell information has been written;

third address formatting means for creating an address signal for accessing all of the addresses of said row failure cell storage means on the basis of the output signals from said flag address generator and said row address generator; and

fourth address formatting means for creating an address signal for accessing all of the addresses of said column failure cell storage means on the basis of the output signals from said flag address generator and said column address generator.

3. The memory testing apparatus according to claim 1, further including:

means for storing therein the total number of failure memory cells read out from one or more memory blocks in which failure memory cell information has been written.

4. The memory testing apparatus according to claim 2, further including:

means for storing therein the total number of failure memory cells read out from one or more memory blocks in which failure memory cell information has been written.

5. The memory testing apparatus according to claim 1, wherein said flag memory is arranged such that at the time of testing a memory under test, it is accessed by an address signal created by said address formatting means whereby a logical value representing a flag is written at an address of said flag memory being accessed by said address signal each time failure cell information is written in said failure analysis memory.

6. The memory testing apparatus according to claim 1, wherein the storage capacity of said flag memory is selected between one in several tens (1/several tens) and one in several thousand (1/several thousand) of that of said failure analysis memory.

7. The memory testing apparatus according to claim 1, wherein said address formatting means takes out most significant several bits from a row address signal and most significant several bits from a column address signal of an address signal applied to said failure analysis memory, respectively, thereby to create an address signal for accessing all of the addresses of said flag memory.