Electronic apparatus, process for its duplication, and arrangement for data transfer between two similarly constructed electronic apparatus

• US 5,832,194 A
• Filed: 09/18/1996
• Issued: 11/03/1998
• Est. Priority Date: 02/24/1996
• Status: Expired due to Fees

• Current Assignee: Hella KGaA Hueck & Company, Mercedes-Benz Bank AG (Mercedes-Benz Group AG)
• Original Assignee: HELLA KG Hueck & Co., Mercedes-Benz AG (Mercedes-Benz Group AG)
• Inventors: Finsterbusch, Joachim, Decius, Nikolaus, Braun, Fritz
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): DARBE, VALERIE A
• Application Number:
  US08/710,512
• Time in Patent Office: 776 Days
• Field of Search: 395/180, 395/182.04, 395/184, 395/185, 395/186, 395/187, 395/750.01
• US Class Current: 714/1
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

An electronic apparatus, process for its duplication, and arrangement for data transfer between two similarly constructed electronic apparatus is described in which the electronic apparatus has a microprocessor or microcontroller, a non-volatile memory, and an interface. The microprocessor or microcontroller, the non-volatile memory and other measures of the apparatus allow a data content of a certain memory component of a certain other apparatus to be simply transferred into the non-volatile memory. The apparatus thus has the ability to bequeath its data characteristics, or to duplicate itself. Further, a process is described for carrying out such a duplication. Assuming a second inventive electronic apparatus is built, a particular advantageous arrangement can be created in which a data record can be completely transferred from the memory of the first apparatus into the memory of the second apparatus. This data transfer is even beneficially possible when the second apparatus is partially defective.

Claims

1. An electronic apparatus (A) including a microprocessor (MP;

MPI,

     10), a non-volatile memory (SP;

SP1) and an interface (I;

KUA, KGNDA, KTA, KDA, KCA), said interface being adapted to be coupled with a second interface (I;

KUB, KGNDB, KTB, KDB) of a second electronic apparatus (B) which is substantially identical in structure to said electronic apparatus (A);

wherein, said electronic apparatus (A) includes an energy supply circuit for;

distributing an intrinsic operating voltage, obtained by said electronic apparatus (A) independently of the interface, to the microprocessor, the non-volatile memory and the interface; and

, distributing an external operating voltage received from said interface to the non-volatile memory;

wherein said electronic apparatus (A) further includes a data transfer circuit for;

retrieving data from a second non-volatile memory of said second electronic apparatus (B) when the second electronic apparatus (B) is coupled to said interface and powered by said intrinsic operating voltage across the interface; and

transmitting data from the non-volatile memory to said substantially-structurally-identical electronic apparatus (B) across said interface when said electronic apparatus (A) receives said external operating voltage from said second electronic apparatus (B) across said interface;

whereby, said electronic apparatus (A) can be coupled to said second electronic apparatus (B) at said interface, can distribute said intrinsic operating voltage to said second non-volatile memory of said second electronic apparatus (B) across said interface for powering said second non-volatile memory, and can retrieve data from said second non-volatile memory to thereby become a replacement electronic apparatus for said second electronic apparatus (B).

2. The electronic apparatus as in claim 1 structured such that when it receives the external operating voltage from the second electronic apparatus (B) across the interface, a data contents of the non-volatile memory (SP;

SP1) of the first apparatus (A) is automatically copied into the second non-volatile memory (SP;

SP2) of the second electronic apparatus (B).

3. The electronic apparatus of claim 1 wherein said data transfer circuit includes a controllable switching arrangement (S) and wherein there is at least one signal lead (D, T) from each of the microprocessor, the non-volatile memory and the interface (MP, SP, I) which is coupled with the controllable switching arrangement (S), and wherein:

the controllable switching arrangement (S) has a plurality of switched positions so that any two respective signal leads from the respective microprocessor, non-volatile memory and interface (MP, SP, I) can be coupled to one another; and

wherein the controllable switching arrangement (S) can be controlled via signals received from the second electronic apparatus across the interface (I) into a switched position in which the switching arrangement (S) couples the at least one signal lead of the non-volatile memory (SP) with the at least one signal lead of the interface (I).

4. The electronic apparatus according to claim 3 wherein said switch is structured such that a logic signal applied to the interface (I) by the second electronic apparatus controls the switching arrangement (S) into a switched position in which it couples the at least one signal lead (D, T) of the non-volatile memory (SP) with the at least one signal lead (D, T) of the interface (I).

5. The electronic apparatus as in claim 3 wherein the external operating voltage (U+, U-) applied to the interface (I) by the second electronic apparatus controls the switching arrangement (S) of the electronic apparatus (A) into the switched position in which it couples the at least one signal lead (D, T) of the non-volatile memory (SP) with the at least one signal lead (D, T) of the interface (I).

6. The electronic apparatus according to claim 3, wherein:

each of the microprocessor (MP), the non-volatile memory (SP) and the interface (I) has only one serial data line (D) and one clock signal line (T).

7. The electronic apparatus as in claim 3, wherein:

the switching arrangement has a first switching device (S1) to switch the at least one signal lead (D, T) of the microprocessor (MP) between the at least one signal leads of the non-volatile memory (SP) and the at least one signal lead (D, T) of the interface (I), this first switching device (S1) being controlled by the microprocessor (MP) via an access control lead (Z1) connected between the microprocessor (MP) and the first switching device S1.

8. The electronic apparatus as in claim 7, wherein:

the switched position of the first switching device (S1) when the microprocessor (MP) does not having a voltage supplied thereto makes possible a coupling of the at least one signal lead (D, T) of the interface (I) with the at least one signal lead of the non-volatile memory (SP).

9. The electronic apparatus as in claim 3, wherein:

the switching arrangement (S) has a second switching device (S2) which makes possible a switching of the at least one signal lead of the interface (I) between the at least one signal lead of the microprocessor (MP) and the at least one signal lead of the non-volatile memory (SP).

10. The electronic apparatus as in claim 9, wherein:

a switched position of the second switching device (S2) depends upon which of the intrinsic operating voltage and the external operating voltage powers the electronic apparatus.

11. The electronic apparatus as in claim 3, wherein:

the interface (I) has a protection circuit for protecting against damaging voltages passing across said interface.

12. The electronic apparatus as in claim 3, wherein:

at least the non-volatile memory (SP) and the switching arrangement (S) can be supplied with energy by the external operating voltage (U+, U-) via the interface (I).

13. The electronic apparatus as in claim 1, wherein:

the interface, in addition to contacts (KUA, KGNDA, KTA, KDA), , includes inter-cooperating structures which make difficult an unintentional and unauthorized access to interface contacts unless these inter-cooperating structures are engaged with one another.

14. The electronic apparatus as claim 13, wherein:

the electronic apparatus (A) has a housing which, relative to its interface and relative to a second housing of the second electronic apparatus (B) and its interface, is so arranged, that the interface and the second interface can be coupled together for transferring data, only by interplugging the two electronic apparatus together.

15. A system as in claim 3 wherein the first and second interfaces (I) of the first and the second electronic apparatus can be coupled together so that when the first electronic apparatus (A) is coupled to an operational voltage source (UB) the second electronic apparatus (B) is supplied with the operational voltage (U+U-)from the first electronic apparatus (A) via the first and second interfaces (I), and so that, through this coupling of the two electronic apparatus (A, B), the first and second switching arrangements (S) of the electronic apparatus (A, B) are respectively each placed in a switched position that a data transfer from the second non-volatile memory (SP) of the second electrical apparatus (B) to the non-volatile memory (SP) of the first electronic apparatus (A) takes place under control of the microprocessor (MP) of the first electronic apparatus (A).

16. The electronic apparatus as in claim 1, wherein:

the interface includes contacts and the electronic apparatus is otherwise so arranged that the interface and the second interface can be plugged directly together without the use of a further intermediate coupling element.

17. The electronic apparatus as in claim 1, wherein:

all hardware elements (12, Z10, R11, R₁₂, R₁₄, R₁₅), other than the microprocessor and non-volatile memory are electronic components having not more than two operating voltage terminals so that all electronic components can be activated by application of only two voltage levels of operating voltage.

18. A system as in apparatus for transfer of data according to claim 17 wherein for each electronic apparatus:

the microprocessor (MP), during a period in which data is written into the non-volatile memory (SP), already reads out data from the non-volatile memory (SP) of another electronic apparatus coupled to its interface.

19. The electronic apparatus as in claim 1, wherein:

said energy supply circuit includes a power supply rail (18) from which the microprocessor is supplied with current and this power supply rail (18) is coupled to an additional energy storer (3) that receives and temporarily stores energy it receives from the intrinsic operating voltage.

20. The electronic apparatus as in claim 1, wherein:

said energy supply circuit includes an operating voltage path and wherein;

an electronic valve (12) is coupled in an operating voltage path between the microprocessor and the non-volatile memory.

21. The electronic apparatus as in claim 20, wherein:

at least a part of a boot-program of the microprocessor (10) is stored in the non-volatile memory (11) which can be supplied with the operating voltage via the interface to the second electronic apparatus.

22. The electronic apparatus as in claim 1, wherein:

the non-volatile memory (11) has an ENABLE- or NOT_-- ENABLE/INHIBIT-Input (11.1) whose status can be inquired and set by the microprocessor.

23. The electronic apparatus as in claim 22, wherein:

said data transfer circuit includes a path (17) for inquiring and setting the ENABLE- or NOT-ENABLE/INHIBIT-input (11.1) which is coupled through a resistor (Z10) with the operating voltage.

24. The electronic apparatus as in claim 1, wherein:

the data transfer circuit includes a data line (13) between the microprocessor and the non-volatile memory which is coupled via a terminal resistor (R₁₂) with a reference potential (GND).

25. Process for copying the contents of a second electronic apparatus (B) which has a second microprocessor (MP2), a second non-volatile memory (SP2) and a second interface (KUB, KGNDB, KTB, KDB), into a first similarly-structured electronic apparatus (A) having a similarly structured first interface, a first microprocessor and a first non-volatile memory (SP1) whereby the first interface is so arranged that it can be coupled with the second interface of the second similarly-structured, electronic apparatus, said process including the following steps:

(1) coupling the first interface of the first electronic apparatus with the second interface of the second electronic apparatus;

(2) applying a normal operational voltage to terminals (K10, K11) of the first electronic apparatus (A);

(3) initially, immediately, deactivating the first non-volatile memory component (11) of the first electronic apparatus (A) in response to this application of voltage and immediately activating the second non-volatile memory component (21) in the second electronic apparatus (B) in response to this application of voltage,

(4) recording with the first microprocessor of the first electronic apparatus (A), data from the second non-volatile memory (SP1) by initiating and carrying out a reading of data from the second non-volatile memory (SP2) of the second electronic apparatus (B) into a working memory area (10.5) of the first microprocessor (10) of the first electronic apparatus (A);

(5) Monitoring, upon completion of this reading, a signal level (DATA;

U_R14), which is positively caused to pass over the first and second interfaces away from the second electronic apparatus (B) into the first electronic apparatus (A), to indicate to the first microprocessor (10) of the first electronic apparatus (A) the existence of a coupling with the second electronic apparatus (B);

(6) Separating the first and second electronic apparatuses (A) and (B), while maintaining the current supply to the first electronic apparatus (A);

(7) Recognizing by means of the level monitoring in step (5) the separation of the interfaces as a true condition for a now possible reverse writing of data previously read into said first working memory area (10.5) of the first microprocessor (10) of the first electronic apparatus (A) into the first non-volatile memory (SP1), of the first electronic apparatus (A);

(8) Initiating and carrying out a reverse writing of said data from the working memory area (10.5) into the first non-volatile memory (SP1) of the first electronic apparatus (A) and waiting until this is completed.

26. Process as in claim 25, wherein is included the further step of

(9) Waiting until the microprocessor (10) has started anew by normally booting up an application of the first electronic apparatus (A) and the first electronic apparatus (A) has thus achieve operability.

27. Process as in claim 26, wherein is included the further step:

(10) Testing during the boot up data which came from the non-volatile memory (21) of the second electronic apparatus (B) into the non-volatile memory (11) of the first electronic apparatus (A) to determine the correctness of the completed data transmission.

28. Process according to claim 26, wherein is included the further step of

(11) Recognizing from an achieved operational readiness of the first electronic apparatus (A), a correctness of the completed data transmission from the non-volatile memory (21) of the second electronic apparatus (B) into the non-volatile memory (11) of the first electronic apparatus (A).

29. The process according to claim 25 wherein the second electronic apparatus B is a production-tool apparatus used during production of new electronic apparatus, and said first electronic apparatus A is a newly produced apparatus.

30. A system comprising a plurality of Electronic apparatus each including a microprocessor (MP;

MPI,

     10), a non-volatile memory (SP;

SP1) and an interface (I;

KUA, KGNDA, KTA, KDA, KCA), with a first interface (I;

KUA, KGNDA, KTA, KDA) of a first electronic apparatus (A) of the system being adapted to be coupled with a corresponding second interface (I;

KUB, KGNDB, KTB, KDB) of a second electronic apparatus (B) of the system;

said first electronic apparatus having a first microprocessor (MP;

MPI,

     10), a first non-volatile memory (SP;

SP1), a first energy supply circuit, and a first data transfer circuit and said second electronic apparatus having a second microprocessor (MP;

MPI,

     10), a second non-volatile memory (SP;

SP1), a second energy supply circuit, and a second data transfer circuit;

wherein, the first energy supply circuit includes first terminals which, when an operating voltage is applied thereto, supplies an operating voltage to the first microprocessor and the first non-volatile memory and, at the same time, supplies an operating voltage to the first interface for thereby supplying an operating voltage to the second electronic apparatus when said first and second interfaces are coupled;

Wherein said second energy supply circuit includes means for powering said second non-volatile memory with an operating voltage received by said second electronic apparatus at said second interface;

wherein said first and second data transfer circuits and said first microprocessor cooperate to transmit data from said second non-volatile memory to said first non-volatile memory across said first and second interfaces when they are coupled, in response to said second non-volatile memory being powered with an operating voltage received from said first energy supply circuit across said first and second interfaces.