Network adapter having single ported memory which is accessible by network and peripheral bus on a time division multiplexed (TDM) basis

• US 5,832,216 A
• Filed: 05/20/1997
• Issued: 11/03/1998
• Est. Priority Date: 11/04/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Szczepanek, Andre
• Primary Examiner(s): AN, MENG AI T
• Application Number:
  US08/859,519
• Time in Patent Office: 532 Days
• Field of Search: 370/391, 370/395, 370/280, 370/314, 370/905, 370/915, 370/916, 395/800.28, 395/800.29, 395/800.36, 395/200.8, 395/309, 395/307, 395/306, 395/287, 711/127, 711/130, 711/131, 711/147, 711/149, 711/157, 711/104
• US Class Current: 709/250
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9089 replacing packets in a storage arrangement, e.g. pushout

Abstract

This invention relates to an improved LAN adapter. The LAN adapter includes a time division multiplex (TDM) ported RAM. The RAM is used to provide both network data FIFOs and control data storage in a single memory element. The network and peripheral components are able to access the same memory, but at different times in the cycle, thereby minimizing the component count and optimizing the operation of the adapter.

Claims

1. An adapter, adapted for connecting an asynchronous data communication network system to a computer peripheral bus having a predetermined width, the adapter comprising a single ported memory having an access port with a width that is at least twice said predetermined width of said peripheral bus, which is accessible, in use, by both the network and peripheral bus on a time division multiplexed (TDM) basis, wherein the peripheral bus is controlled by a clock having cycles and the single ported memory is accessed by the network and the peripheral component on different clock cycles according to a predetermined relationship.

2. An adapter according to claim 1, wherein a local processor is also accessible to the single ported memory by way of a bus internal to the adapter.

3. An adapter as claimed in claim 1, wherein said predetermined relationship is that the single ported memory is accessed by the network on every other clock cycle and the peripheral component during the other clock cycles.

4. An adapter according to claim 1, wherein the single ported memory comprises a RAM.

5. An adapter according to claim 1, wherein the single ported memory comprises an SRAM.

6. An adapter according to claim 1, wherein the adapter is connected between a Local Area Network (LAN) and a peripheral component interface (PCI) bus.

7. An adapter according to claim 6, further comprising a PCI controller connecting the single ported to the PCI bus.

8. An adapter according to claim 7, further comprising a LAN controller connecting the single ported to the LAN.

9. An adapter according to claim 1, further comprising FIFO control registers operable to cause the single ported to implement a circular buffer FIFO effect.

10. A method of effecting communication between an asynchronous data communication network and a computer peripheral bus operating under control of a clock having cycles and having a predetermined width, comprising:

connecting an adapter between the network and the peripheral bus, said adapter comprising a single ported memory having an access port with a width that is at least twice said predetermined width of said peripheral bus, and which is accessible, in use, by both the network and the peripheral bus on a time multiplexed basis;

allowing the network to access the single ported memory on every other clock cycle; and

allowing the bus to access the single ported memory during the other clock cycles thereby effecting data and control storage during the respective clock cycles.