Power control apparatus for digital electronic device

• US 5,832,286 A
• Filed: 05/23/1995
• Issued: 11/03/1998
• Est. Priority Date: 12/04/1991
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Yoshida, Yukihiro
• Primary Examiner(s): Stamber, Eric W.
• Application Number:
  US08/447,734
• Time in Patent Office: 1,260 Days
• Field of Search: 364/483, 364/492, 364/707, 364/948.4, 364/948.5, 364/948.6, 364/948.7, 364/948.8, 364/948.9, 364/948.91, 395/750, 365/230.03, 307/30, 307/31, 307/32, 307/33, 307/34, 307/35, 307/36, 307/37, 307/38, 307/39, 307/40, 307/41
• US Class Current: 713/324
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A power control apparatus for controlling power used by a digital electronic device having a plurality of processing devices for example, a CPU and a plurality of I/O controllers as well as a memory for storing power control instructions. The CPU is configured to output power control signals via one of the I/O controllers based on the signals or power control instructions. A microcomputer is provided to which the power control signals are input and which are configured to control power and clock frequency supplied to each one of the plurality of processing devices based on the power control signals. The microcomputer detects the input of the power control signal, sets power control bits for the plurality of processing devices into a data register based on the detection, and outputs via the I/O port the contents of the data register to control the power to each of the plurality of processing devices.

Claims

1. A power control apparatus for individually controlling power used by a digital electronic device for respective one of a plurality of processing devices composing the electronic device together with a memory and including a CPU and a plurality of I/O controllers, said plurality of processing devices having a plurality of operational modes and said memory having a region storing a power management program composed of power control instructions prepared according to a function of at least one of a plurality of operational modes of each processing device for which electric power is to be individually controlled, said CPU configured to output power control signals via one of the I/O controllers based on said power control instruction, said apparatus comprising:

a microcomputer unit to which said power control signals are input and which is configured to control power and clock frequency supplied to each one of said plurality of processing devices based on said power control signals, said microcomputer unit comprising;

means for detecting the input of said power control signals;

a data register for storing power control data for said plurality of processing devices;

means for setting power control bits for said plurality of processing devices into said data register based on the detecting performed by the means for detecting; and

output means for outputting the contents of the data register to control the power to each of said plurality of processing devices.

2. A power control apparatus according to claim 1 wherein said microcomputer is configured to output a plurality of clock control signals based on said power control signals.

3. A power control apparatus according to claim 1 wherein said microcomputer includes:

an I/O port for receiving said power control signals;

a read only memory in which a program for monitoring the reception of said power control signals is stored; and

another I/O port for outputting the contents of said data register.

4. A power control apparatus according to claim 1 further including a plurality of switching means each connected to each of said plurality of processing devices for selectively supplying one of a plurality of power voltages to each of said plurality of processing devices based on the output from said microcomputer.

5. A power control apparatus according to claim 4 wherein each of said plurality of switching means may comprise a plurality of transistors connected to different power supplies, and the output from the microcomputer is input to the base of each of the transistors.

6. A power control apparatus according to claim 1 wherein said plurality of processing devices are configured to receive a plurality of voltages from a common power supply, and said power control apparatus further includes a single switching device for selectively supplying one of said plurality of voltages from the common power supply to said plurality of processing devices as a common voltage, based the output from said microcomputer.

7. A power control apparatus according to claim 1 further including a plurality of switching means for individually controlling powers to part of said plurality of processing devices and another switching means for commonly controlling powers to part of said plurality of processing devices.

8. A digital electronic device system with a power control function for individually controlling power used by

a digital electronic device for respective one of a plurality of processing devices composing the electronic device together with a memory including a CPU and a plurality of I/O controllers said plurality of processing devices having a plurality of operational modes and said memory having a region storing a power management program composed of power control instructions prepared according to a function of at last one of plurality of operational modes of each processing device for which electric power is to be individually controlled said CPU configured to output power control signals via one of the I/O controllers based on the power control instructions said apparatus comprising:

a power control apparatus for controlling power used by the digital electronic device, the power control apparatus including a microcomputer unit to which said power control signals are input and which are configured to control power and clock frequency supplied to each one of said plurality of processing devices based on said power control signals, said microcomputer unit comprising;

means detecting the input of said power control signals;

a data register for storing power control data for said plurality of processing devices;

means for setting power control bits for said plurality of processing devices into said data register based on said detecting performed by the means for detecting; and

output means for outputting the contents of the data register to control the power to each of said plurality of processing devices.

9. A digital electronic device system according to claim 8 wherein said digital electronic device and said power control apparatus are integrated on a single chip.

10. A digital electronic device system according to claim 8 wherein the power control instruction stored in said memory comprises an instruction for controlling supply of the power and an instruction for varying the clock frequency.