Apparatus, systems and method for improving memory bandwidth utilization in vector processing systems

• US 5,832,290 A
• Filed: 01/17/1997
• Issued: 11/03/1998
• Est. Priority Date: 06/13/1994
• Status: Expired due to Term

• Current Assignee: HTC Corporation
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Gostin, Gary B., Barr, Matthew F., McGuffey, Ruth A., Roan, Russell L.
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US08/785,192
• Time in Patent Office: 655 Days
• Field of Search: 365/236, 365/230.05, 711/217, 711/218, 711/219, 711/220, 395/800.04, 395/800.05, 395/800.06
• US Class Current: 712/5
• CPC Class Codes: G06F 15/8076 Details on data register access
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06

Abstract

Vector register circuitry is provided which includes a vector register file comprising at least one vector register having a plurality of elements, the vector register file further having at least one data port and at least one address port for accessing selected ones of the elements of the vector register. Address generation circuitry is provided coupled to the address port and includes an adder having an output coupled to the address port, a first element register having an output coupled to a first input of the adder and an element counter having an output coupled to a second input of the adder.

Claims

1. Vector register circuitry comprising:

a vector register file comprising at least one vector register having a plurality of elements, said register file having at least one data port and at least one address port for accessing selected ones of said elements of said vector register; and

address generation circuitry coupled to said at least one address port comprising;

an adder having an output coupled to said address port;

a first element register having an output coupled to a first input of said adder;

an element counter having an output coupled to a second input of said adder; and

a vector mask register having an output directly connected to an input of said element counter.

2. The circuitry of claim 1 and further comprising a vector first register having an output coupled to said first element register.

3. The circuitry of claim 1 wherein said data port comprises a write data port.

4. The circuitry of claim 1 wherein said data port comprises a read data port.

5. Vector register circuitry comprising:

a vector register comprising a plurality of elements and associated with at least one data port and at least one address port for accessing selected ones of said elements; and

address generation circuitry comprising;

an element register for holding a value representing a first said element to be accessed;

a counter incrementing in response to a clock signal;

a mask register for holding a mask, said mask directly presented to said counter such that said counter increments through a noncontinuous sequence of counts; and

an adder coupled to said address port for adding said value held in said element register with count from said counter to generate sequence of addresses corresponding to said selected ones of said elements.

6. The circuitry of claim 5 and further comprising a vector first register coupled to said element register, said value transferred from said vector first register to said element register prior to the generation of a first said address.

7. The circuitry of claim 5 wherein said vector register is one of a plurality of vector registers disposed within a vector register file.

8. The circuitry of claim 5 wherein said data port comprises a read data port for reading data from said selected ones of said elements.

9. The circuitry of claim 5 wherein said data port comprises a write data port for writing data to said selected ones of said elements.

10. Vector register circuitry comprising:

a vector register file comprising a plurality of vector registers, each said vector register having a plurality of elements, said register file having at least one write data port and an associated write address port for writing data into selected ones of said elements and at least one read data port and an associated read address port for reading data from selected ones of said elements;

processing circuitry coupled to said read data port and said write data port;

write address generation circuitry coupled to said write address port comprising;

a first element register for holding a value representing a first said element to be written to;

a counter incrementing in response to a clock signal;

a mask register for holding a mask, said mask directly presented to said counter such that said counter increments through a noncontinuous sequence of counts; and

an adder for adding said value held in said first element register with a count from said counter to generate at least one address corresponding to at least one said element to be written to through said address port; and

read address generation circuitry coupled to said read address port comprising;

a first element register for holding a value representing a first said element to be accessed;

a counter incrementing in response to a clock signal;

a mask register for holding a mask, said mask directly presented to said counter such that said counter increments through a noncontinuous sequence of counts; and

an adder for adding said value held in said first element register with a count from said counter to generate at least one address corresponding to at least one said element to be read from through said at least one address port.

11. The circuitry of claim 10 wherein said processing circuitry comprises functional circuitry operable to perform arithmetic and logic operations.

12. The circuitry of claim 11 wherein said processing circuitry receives operands from said at least one read data port and sends results to said at least one write data port.

13. The circuitry of claim 12 wherein said processing circuitry includes interface circuitry for exchanging operands and results with an associated main memory.

14. The circuitry of claim 10 wherein said vector register circuitry forms a portion of a vector processor.

15. The circuitry of claim 10 wherein said vector registers of said vector register files are organized as a plurality of banks of vector registers, each said bank associated with at least one said read port and at least one said write port.