Process for producing a luminous element of group III nitride semi-conductor

• US 5,834,326 A
• Filed: 12/11/1996
• Issued: 11/10/1998
• Est. Priority Date: 12/12/1995
• Status: Expired due to Term

• Current Assignee: Showa Denko KK (Resonac Holdings Corp.)
• Original Assignee: Pioneer Electronic Corporation (Pioneer Corporation)
• Inventors: Takahashi, Hirokazu, Watanabe, Atsushi, Ota, Hiroyuki, Sato, Hitoshi, Tanaka, Toshiyuki, Kimura, Yoshinori, Miyachi, Mamoru, Amano, Hiroshi, Akasaki, Isamu
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Pham, Long
• Application Number:
  US08/763,779
• Time in Patent Office: 699 Days
• Field of Search: 438/29, 438/46, 438/509, 438/796, 148/DIG. 65, 148/DIG. 113
• US Class Current: 438/29
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/325 characterised by the doping materials
• CPC Class Codes: Y10S 148/065 Gp III-V generic compounds-processing
• CPC Class Codes: Y10S 148/113 Nitrides of boron or aluminum or gallium

Abstract

A process for producing a semiconductor emitting device of group III nitride semiconductor having a crystal layer (Al_x Ga_1-x)_1-y In_y N (0≦x≦1, 0≦y≦1) includes; a step of forming at least one pn-junction or pin-junction and a crystal layer (Al_x Ga_1-x)_1-y In_y N (0≦x≦1, 0≦y≦1) to which a group II element is added; and a step of forming electrodes on the crystal layer. The process further includes an electric-field-assisted annealing treatment in which the pn-junction or pin-junction is heated to the predetermined temperature range while forming and maintaining an electric field across the pn-junction or pin-junction for at least partial time period of the predetermined temperature range via the electrodes.

Claims

1. A process for producing a semiconductor emitting device of group III nitride semiconductor having a substrate, comprising the steps of:

forming an n-type crystal layer of (Al_x Ga_1-x)_1-y In_y N(0≦

x≦

1, 0≦

y≦

1) and a p-type crystal layer of (Al_x G_1-x)_1-y In_y N (0≦

x≦

1, 0≦

y≦

1) having an added group II element over said substrate to form at least one pn-junction or pin-junction;

forming electrodes on said crystal layers; and

heating said pn-junction or pin-junction to a temperature range of room temperature or more while forming, supplying and maintaining an electric field across said pn-junction or pin-junction during maintenance of said temperature range via said electrodes.

2. A process according to claim 1, wherein said junction forming step includes a metalorganic chemical vapor deposition method in which by using one set of metalorganic compound gases, an n-type crystal layer of group III nitride semiconductor (Al_x Ga_1-x)_1-y In_y N (0≦

x≦

1, 0≦

y≦

1) is formed over said substrate and then a p-type crystal layer of group III nitride semiconductor (Al_x Ga_1-x)_1-y In_y N (0≦

x≦

1, 0≦

y≦

1) is formed on said n-type crystal layer.

3. A process according to claim 2, wherein said heating step is performed at said temperature range ranging from 100°

C. to 600°

C.

4. A process according to claim 2, wherein at least one of said electrodes is formed of a hydrogen-permeable metal having a hydrogen-permeability at said temperature range, and then said electric field is formed by applying a voltage across said n-type crystal layer and said electrodes in a reverse bias for the pn-junction or pin-junction in said heating step.

5. A process according to claim 2, wherein said electric field is formed by applying a voltage across said n-type crystal layer and said electrodes in a forward bias for the pn-junction or pin-junction in said heating step.

6. A process according to claim 5, wherein said applied voltage is 1.5V or more.

7. A process according to claim 5, wherein, in said heating step, said voltage across said n-type crystal layer and said electrodes is supplied from a constant-current source, and said n-type crystal layer and said electrodes are connected in parallel to voltage limiting means for restricting an upper limit of said applied voltage.

8. A process according to claim 7, further comprising a step of superposing an AC current to electric current supplied from said constant-current source.

9. A process according to claim 3, wherein at least one of said electrodes is formed of a hydrogen-permeable metal having a hydrogen-permeability at said temperature range, and then said electric field is formed by applying a voltage across said n-type crystal layer and said electrodes in a reverse bias for the pn-junction or pin-junction in said heating step.

10. A process according to claim 3, wherein said electric field is formed by applying a voltage across said n-type crystal layer and said electrodes in a forward bias for the pn-junction or pin-junction in said heating step.

11. A process according to claim 10, wherein said applied voltage is 1.5V or more.

12. A process according to claim 10, wherein, in said heating step, said voltage across said n-type crystal layer and said electrodes is supplied from a constant-current source, and said n-type crystal layer and said electrodes are connected in parallel to voltage limiting means for restricting an upper limit of said applied voltage.

13. A process according to claim 12, further comprising a step of superposing an AC current to electric current supplied from said constant-current source.