Method of forming a multi-chip module from a membrane circuit

• US 5,834,334 A
• Filed: 06/07/1995
• Issued: 11/10/1998
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn Joseph
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/484,144
• Time in Patent Office: 1,252 Days
• Field of Search: 437/205, 437/206, 437/208, 437/209, 438/107, 438/14, 438/17, 438/117, 438/123
• US Class Current: 438/107
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136281 having a transmissive semiconductor substrate
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/135 : Removal of substrate
• CPC Class Codes: Y10S 438/928 : Front and rear surface processing
• CPC Class Codes: Y10S 438/938 : Lattice strain control or utilization
• CPC Class Codes: Y10S 438/942 : Masking
• CPC Class Codes: Y10S 438/967 : Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49171 : with encapsulating
• CPC Class Codes: Y10T 29/4921 : with bonding

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Claims

1. A method of testing an integrated circuit having electrical contracts formed thereon spaced apart a distance of less than about 50 μ

m, comprising the steps of;

providing a flexible tester membrane including a plurality of probe points formed on one surface thereof, and a plurality of integrated circuits attached to an opposing surface thereof for providing test signals to the probe points;

electrically interconnecting the integrated circuits to the probe points by conductors extending through the tester membrane; and

providing at least two of the probe points spaced apart less than about 50 μ

m.

2. The device of claim 1, wherein at least two of the probe points are spaced apart by less than about 2 μ

m.

3. A method of forming a multi-chip module using a flexible inorganic membrane to interconnect the chips, comprising the steps of:

providing a flexible inorganic membrane;

forming conductive traces on the membrane; and

mounting a plurality of integrated circuit die to the membrane at the traces.

4. The method of claim 3, further comprising the steps of:

forming a dielectric layer on the membrane; and

forming additional metal traces on the dielectric layer.

5. The method of claim 3, further comprising the step of providing a support ring attached to the edge of the membrane.

6. The method of claim 5, wherein the step of mounting comprises the steps of:

enclosing the membrane and support ring in a housing; and

providing pressure in the housing to keep the membrane in contact with the integrated circuit die.

7. The method of claim 3, further comprising the step of forming a hermetic seal between a surface of each die and the membrane.

8. The method of claim 3, wherein the step of mounting comprises the steps of:

providing a plurality of recesses in a surface of the membrane, each recess being associated with a bonding pad on one of the integrated circuit die;

providing a solder bump on one of each bonding pad or the bottom of the associated recess; and

forming a solder weld bond between each bonding pad and the associated recess by applying heat to the membrane.

9. The method of claim 8, wherein the heat is applied to a surface of the membrane opposite to that in which the recesses are formed.

10. The method of claim 8, wherein the die bonding pads are each less than about 2 mils in diameter.

11. A method of bonding an integrated circuit die to a flexible membrane, comprising the steps of:

providing an integrated circuit die having at least one bonding pad formed overlying semiconductor devices of the integrated circuit die; and

attaching the integrated circuit die to the flexible membrane by bonding the bonding pads to electrical traces on the membrane.

12. The method of claim 11, wherein the step of attaching comprises:

pressing the integrated circuit die against a surface of the membrane;

providing solder at a point to be bonded;

applying pressure to an opposing surface of the membrane; and

heating the opposing surface of the membrane.

13. The method of claim 11, further comprising the step of hermetically bonding an edge of the integrated circuit die to the membrane.

14. A method of testing an integrated circuit comprising:

providing a flexible free standing circuit membrane including a semiconductor layer and a flexible low stress dielectric layer, and having at least 100 probe points formed on its principal surface;

providing a source of pressure against a back surface of the membrane, thereby contacting the integrated circuit being tested with the probe points; and

moving the integrated circuit being tested laterally relative to the circuit membrane while in contact with the probe points.

15. The method of claim 14, wherein the lateral motion is less than about 100 μ

m and is repeated.