MOSFET having tapered gate electrode

• US 5,834,816 A
• Filed: 03/10/1997
• Issued: 11/10/1998
• Est. Priority Date: 10/10/1991
• Status: Expired due to Term

• Current Assignee: Goldstar Electronics Co., Limited (LG Corporation), Goldstar Electron Co., Ltd. (SK Hynix Inc.)
• Original Assignee: Goldstar Electron Co., Ltd. (SK Hynix Inc.)
• Inventors: Jang, Seong Jin
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/816,009
• Time in Patent Office: 610 Days
• Field of Search: 257/288, 257/368, 257/382, 257/384, 257/401, 257/412, 257/768, 257/344
• US Class Current: 257/382
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76889 by forming silicides of refractory metals
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/117 Oxidation, selective

Abstract

A MOSFET comprising a gate oxide layer on a silicon substrate, a polysilicon gate formed on the gate oxide layer, the length of which gradually widens going from bottom to top, a side gate oxide layer formed by an oxidation process surrounding the polysilicon gate, the side gate oxide layer also gradually widening from bottom to top, a source/drain region beside the gate oxide layer, a connection element having a stacked structure of a polysilicon and/or polycide layer on the field oxide, a doped polysilicon side wall beside the side gate oxide layer and making electric connection between the source/drain region and the connection element.

Claims

1. A MOSFET, comprising:

a substrate;

isolation regions formed on the substrate to define an active region in the substrate, the isolation regions comprising a field oxide having a tapered edge adjacent to the active region;

a gate insulating layer formed on the active region;

a tapered gate electrode having first and second sides formed on the gate insulating layer, wherein the top length of the gate electrode is greater than the bottom length of the gate electrode;

first and second tapered conductive regions formed on the substrate and each having a side gate insulating layer formed on each of the first and second tapered conductive regions, wherein the side gate insulating layers and the first and second tapered conductive regions extend to a height greater than the gate electrode, wherein each of the first and second tapered conductive regions is adjacent to a respective side of the tapered gate electrode and extend over the field oxide, and a top insulating layer having a flattened top surface formed over the gate electrode, the side gate insulating layers and the first and second tapered conductive regions, wherein the top insulating layer, the side gate insulating layers and the gate insulating layer insulate the gate electrode;

a source region and a drain region each formed in the substrate beneath a bottom surface of a respective one of the first and second tapered conductive regions; and

first and second stacked conducting layers formed on the field oxide, each of the first and second stacked conducting layers abutting a respective one of the first and second tapered conductive regions and making electrical connection with the respective one of the tapered conductive regions and to the respective source region and drain region.

2. The MOSFET of claim 1, wherein the source and drain regions comprise diffusions of impurities from the tapered conductive regions.

3. The MOSFET of claim 1, wherein the first and second stacked conducting layers each comprise a polysilicon layer.

4. The MOSFET of claim 1, wherein the first and second stacked conducting layers each comprise a polycide layer.

5. The MOSFET of claim 1 further comprising a wiring layer connected to each of the first and second stacked conducting layers.

6. A MOSFET comprising:

a gate oxide layer on a silicon substrate and diffusion source/drain regions formed in the silicon substrate beside the gate oxide layer, and a field oxide formed on the silicon substrate, the field oxide having a tapered edge adjacent to each of the source/drain regions;

a polysilicon gate formed on the gate oxide layer, wherein the polysilicon gate extends between the source/drain regions and has a side extending above each of the source/drain regions, wherein the length of the polysilicon gate in cross section gradually widens from bottom to top;

side gate oxide layers formed by oxidation of polysilicon layers adjacent to the sides of the polysilicon gate, wherein the polysilicon layers and side gate oxide layers extend to a height greater than the polysilicon gate, wherein the polysilicon layers extend over and are electrically connected to the source/drain regions, wherein each of the polysilicon layers has a flattened top surface and also extends over the tapered edge of the field oxide, and a top oxide layer having a flattened top surface formed over the polysilicon gate, the side gate oxide layers and the polysilicon layers, wherein the top oxide layer, the side gate oxide layers and the gate oxide layer surround and insulate the polysilicon gate;

stacked conducting layers formed on the field oxide, each of the stacked conducting layers abutting a corresponding one of the polysilicon layers and having a flattened surface of about the same level as the flattened top surface of the corresponding polysilicon layer and making electrical connection with the corresponding polysilicon layer, wherein each of the stacked conducting layers comprise a polycide layer; and

a metal wiring layer selectively formed over each of the stacked conducting layers and making electrical connection to each of the stacked conducting layers through a corresponding contact hole in the top oxide layer.

7. A MOSFET comprising;

a substrate;

isolation regions formed on the substrate to define an active region in the substrate, the isolation regions comprising a field oxide having a tapered edge adjacent to the active region;

a gate insulating layer formed on the active region;

a gate electrode having first and second sides formed on the gate insulating layer, wherein the length of the gate electrode in cross section gradually widens from bottom to top of the gate electrode;

first and second impurity diffusion regions formed in the substrate beside the first and second sides, respectively, of the gate electrode in the active region adjacent to the field oxide;

side gate oxide layers formed by oxidation of first and second polysilicon layers adjacent to the first and second sides, respectively, of the gate electrode, wherein the side gate oxide layers and the first and second polysilicon layers extend to a height greater than the gate electrode, wherein each of the first and second polysilicon layers is electrically connected to and extend over a respective one of the first and second impurity diffusion regions and each has a flattened top surface and extend over the tapered edge of the field oxide, and a top oxide layer having a flattened top surface formed over the gate electrode, the side gate oxide layers and the first and second polysilicon layers, wherein the top oxide layer, the side gate oxide layers and the gate insulating layer surround and insulate the gate electrode;

first and second stacked conducting layers formed on the field oxide, each of the first and second stacked conducting layers abutting a respective one of the first and second polysilicon layers and having a flattened surface of about the same level as the flattened top surface of the respective one of the first and second polysilicon layers and making electrical connection with the respective one of the first and second polysilicon layers, wherein each of the first and second stacked conducting layers comprise a polycide layer; and

a metal wiring layer selectively formed over each of the first and second stacked conducting layers and making electrical connection to each of the first and second stacked conducting layers through a corresponding contact hole in the top oxide layer, wherein the metal wiring layer is electrically connected to each of the first and second impurity regions of the MOSFET.

8. A MOSFET as claimed in claim 7, wherein the gate electrode comprises polysilicon.

9. A MOSFET as claimed in claim 7, wherein the first and second stacked conducting layers each comprise polysilicon.

10. A MOSFET as claimed in claim 7, wherein the first and second stacked conducting layers each comprise a conducting polysilicon layer connected to a respective one of the first and second impurity diffusion regions, wherein each of the conducting polysilicon layers is electrically connected to the corresponding polycide layer.

11. A MOSFET comprising;

a substrate;

isolation regions formed on the substrate to define an active region in the substrate, the isolation regions comprising a field oxide having a tapered edge adjacent to the active region;

a gate insulating layer formed on the active region;

a gate electrode having first and second sides formed on the gate insulating layer, wherein the top length of the gate electrode is greater than the bottom length of the gate electrode;

first and second impurity diffusion regions formed in the substrate beside the first and second sides, respectively, of the gate electrode in the active region adjacent to the field oxide;

first and second side gate oxide layers formed by oxidation of first and second polysilicon layers adjacent to the first and second sides, respectively, of the gate electrode, wherein the first and second side gate oxide layers and the first and second polysilicon layers extend to a height greater than the gate electrode, wherein each of the first and second polysilicon layers is electrically connected to and extend over a respective one of the first and second impurity diffusion regions and extend over the tapered edge of the field oxide, and a top oxide layer having a flattened top surface formed over the gate electrode, the side gate oxide layers and the first and second polysilicon layers, wherein the top oxide layer, the side gate oxide layers and the gate insulating layer surround and insulate the gate electrode;

first and second stacked conducting layers formed on the field oxide, each of the first and second stacked conducting layers abutting a respective one of the first and second polysilicon layers and making electrical connection with the respective one of the first and second polysilicon layers, and a metal wiring layer selectively formed over each of the first and second stacked conducting layers and making electrical connection to each of the first and second stacked conducting layers through a corresponding contact hole in the top oxide layer, wherein the metal wiring layer is electrically connected to each of the first and second impurity regions of the MOSFET.

12. A MOSFET as claimed in claim 11, wherein the gate electrode comprises polysilicon.

13. A MOSFET as claimed in claim 11, wherein the first and second stacked conducting layers each comprise polysilicon.

14. A MOSFET as claimed in claim 11, wherein the first and second stacked conducting layers each comprise a conducting polysilicon layer electrically connected to a respective one of the first and second impurity diffusion regions, wherein each of the conducting polysilicon layers is electrically connected to a polycide layer.