Field effect transistor with a shaped gate electrode

• US 5,834,817 A
• Filed: 12/01/1992
• Issued: 11/10/1998
• Est. Priority Date: 09/08/1988
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ozaki, Hiroji, Eimori, Takahisa, Satoh, Shinichi
• Primary Examiner(s): BROWN, PETER T
• Application Number:
  US07/983,931
• Time in Patent Office: 2,170 Days
• Field of Search: 257/387, 257/412, 257/413, 257/754-756
• US Class Current: 257/387
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer

Abstract

A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source·drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

Claims

1. A field effect transistor comprising:

a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type;

impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, said impurity layers constituting source-drain regions, each of the impurity layers comprising a first impurity layer portion having a first impurity concentration and a second impurity layer portion having a second impurity concentration which is higher than the first impurity concentration, the first impurity layer portions defining a first channel region at the main surface of the substrate and the second impurity layer portions defining a second channel region, the first impurity layer portions being shallower throughout the substrate as compared with the second impurity layer portions; and

a shaped conductive layer formed by etching on said first channel region with an insulating film interposed therebetween at said main surface, said shaped conductive layer having an upper portion and a lower portion, the upper portion having a flat upper surface and being longer than the lower portion, the length of the lower portion adjacent the insulating film being substantially equal to or shorter than the length of said first channel region, the width of the second channel region being no greater than the length of the upper portion upper surface, and the upper and lower portions being formed of the same material, with the lower portion having a faster etch rate as compared with an etch rate of the upper portion under the same etching conditions, and wherein there is only insulating film between outermost ends of the shaped conductive layer upper portion and the main surface of the substrate, wherein the lower portion of the shaped conductive layer includes a section having tapered side walls.

2. A field effect transistor as defined by claim 1, wherein the shaped conductive layer is T-shaped.

3. A field effect transistor as defined by claim 1, wherein the lower portion further includes a section having vertical side walls.

4. A field effect transistor as defined by claim 1, wherein the upper and lower portions of the shaped conductive layer are formed of polysilicon.

5. A field effect transistor as defined by claim 1, wherein the distance between the upper portion and the main surface of the substrate is greater than the distance between the lower portion and the main surface of the substrate.