In-rush current reduction circuit for boost converters and electronic ballasts

• US 5,834,924 A
• Filed: 03/05/1997
• Issued: 11/10/1998
• Est. Priority Date: 09/29/1995
• Status: Expired due to Term

• Current Assignee: OSRAM Sylvania Inc. (Ams-Osram AG)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Labudda, Kenneth D., Stephens, Dennis L., Konopka, John G., Upadhyay, Anand K.
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US08/811,862
• Time in Patent Office: 615 Days
• Field of Search: 323/222, 323/282, 323/908, 363/56, 363/49, 363/53, 361/58, 361/111, 315/206
• US Class Current: 323/222
• CPC Class Codes: H02H 9/001 limiting speed of change of electric quantities, e.g. soft switching on or off progressive control of electronic switches for eliminating interferences H03K17/16
• CPC Class Codes: H02M 7/062 Avoiding or suppressing excessive transient voltages or currents
• CPC Class Codes: H05B 41/2856 against internal abnormal circuit conditions
• CPC Class Codes: Y10S 323/908 Inrush current limiters

Abstract

An electronic power supply circuit (50) that includes a rectifying circuit (14), a boost converter (16), an in-rush current reduction circuit (52), and a bulk capacitor (18). The in-rush current reduction circuit (52) includes an in-rush current limiting resistor (54) and a bypass capacitor (56) that are connected in parallel with each other. An improved version of the in-rush current reduction circuit (52) includes a bypass diode (58) connected in parallel with the in-rush current limiting resistor (54) and bypass capacitor (56) which is oriented to provide a path for current flowing out of bulk capacitor (18). One particular application of the disclosed circuit is for use in an electronic ballast for fluorescent lamps.

Claims

1. An electronic power supply circuit, comprising:

a rectifying circuit having a pair of input terminals for receiving a source of alternating current and having a pair of output terminals;

a boost converter having a pair of input terminals and having a pair of output terminals, the input terminals of the boost converter being coupled to the output terminals of the rectifying circuit; and

a series circuit that is coupled across the output terminals of the boost converter and that includes a passive in-rush current reduction circuit and a bulk capacitor, the passive in-rush current reduction circuit comprising an in-rush current limiting resistor and a bypass capacitor connected in parallel with each other, wherein;

the in-rush current limiting resistor and the bypass capacitor are coupled between the bulk capacitor and a first output terminal of the boost converter;

the bulk capacitor is coupled between the in-rush current reduction circuit and a second output terminal of the boost converter;

an in-rush current flows into the bulk capacitor for a predetermined transient period following initial application of power to the power supply, the in-rush current having a peak value;

the boost converter supplies a high frequency current to the bulk capacitor during steady-state operation of the power supply; and

the passive in-rush current reduction circuit includes;

a transient mode wherein, following initial application of power to the power supply, a substantial portion of the in-rush current flows through the in-rush current limiting resistor, thereby effecting a reduction in the peak value of the in-rush current; and

a steady-state mode wherein a substantial portion of the high frequency current supplied to the bulk capacitor by the boost converter flows through the bypass capacitor, thereby effecting a reduction in the steady-state power dissipated in the in-rush current limiting resistor.

2. The circuit of claim 1, wherein the in-rush current reduction circuit includes a bypass diode connected in parallel with the in-rush current limiting resistor and the bypass capacitor, wherein the bypass diode is oriented to provide a path around the in-rush current limiting resistor for current flowing out of the bulk capacitor.

3. The circuit of claim 1, wherein the boost converter comprises:

a boost inductor connected between a first node and a second node, and the first node is coupled to the first input terminal of the boost converter;

a boost switch connected between the second node and a third node, and the third node is coupled to the second input terminal of the boost converter and the second output terminal of the boost converter;

a boost rectifier connected between the second node and a fourth node, and the fourth node is coupled to the first output terminal of the boost converter; and

a control circuit for driving the boost switch.

4. The circuit of claim 1, wherein the rectifying circuit comprises a full-wave diode bridge.

5. The circuit of claim 1, wherein the output terminals of the boost converter are adapted to having a load connected across them.

6. The circuit of claim 1, wherein the bypass capacitor has a predetermined capacitance to provide a low impedance path around the in-rush current limiting resistor for high frequency current flowing into the bulk capacitance.

7. The circuit of claim 6, wherein the resistance of the in-rush current limiting resistor is in the range of about 0.1 ohm to about ten thousand ohms, and the capacitance of the bypass capacitor is in the range of about 0.1 microfarad to about 10 microfarads.

8. An electronic power supply circuit, comprising:

a rectifying circuit having a pair of input terminals for receiving a source of alternating current and having a pair of output terminals, wherein the rectifying circuit comprises a full-wave diode bridge;

a boost converter having a pair of input terminals and having a pair of output terminals, the input terminals of the boost converter being coupled to the output terminals of the rectifying circuit, wherein the output terminals of the boost converter are adapted to having a load connected between them, and wherein the boost converter comprises;

a boost inductor connected between a first node and a second node, wherein the first node is coupled to a first input terminal of the boost converter;

a boost switch connected between the second node and a third node, wherein the third node is coupled to a second input terminal of the boost converter and a second output terminal of the boost converter;

a boost rectifier connected between the second node and a fourth node, wherein the fourth node is coupled to a first output terminal of the boost converter; and

a control circuit for driving the boost switch; and

a series circuit that is coupled across the output terminals of the boost converter and that includes a passive in-rush current reduction circuit and a bulk capacitor, the passive in-rush current reduction circuit comprising an in-rush current limiting resistor and a bypass capacitor connected in parallel with each other, wherein;

the in-rush current limiting resistor and the bypass capacitor are coupled between the bulk capacitor and the first output terminal of the boost converter;

the bulk capacitor is coupled between the in-rush current reduction circuit and the second output terminal of the boost converter;

an in-rush current flows into the bulk capacitor for a predetermined transient period following initial application of power to the power supply, the in-rush current having a peak value;

the boost converter supplies a high frequency current to the bulk capacitor during steady-state operation of the power supply; and

the passive in-rush current reduction circuit includes;

a transient mode wherein, following initial application of power to the power supply, a substantial portion of the in-rush current flows through the in-rush current limiting resistor, thereby effecting a reduction in the peak value of the in-rush current; and

a steady-state mode wherein a substantial portion of the high frequency current supplied to the bulk capacitor by the boost converter flows through the bypass capacitor, thereby effecting a reduction in the steady-state power dissipated in the in-rush current limiting resistor.

9. The circuit of claim 8, wherein the in-rush current reduction circuit includes a bypass diode connected in parallel with the in-rush current limiting resistor and the bypass capacitor, wherein the bypass diode is oriented to provide a path around the in-rush current limiting resistor for current flowing out of the bulk capacitor.

10. An electronic ballast for powering gas discharge lamps, comprising:

a rectifying circuit having a pair of input terminals for receiving a source of alternating current and having a pair of output terminals;

a boost converter having a pair of input terminals and having a pair of output terminals, the input terminals of the boost converter being coupled to the output terminals of the rectifying circuit;

a series circuit that is coupled across the output terminals of the boost converter and that includes a passive in-rush current reduction circuit and a bulk capacitor, the passive in-rush current reduction circuit comprising an in-rush current limiting resistor and a bypass capacitor connected in parallel with each other, wherein;

the in-rush current limiting resistor and the bypass capacitor are coupled between the bulk capacitor and a first output terminal of the boost converter;

the bulk capacitor is coupled between the in-rush current reduction circuit and a second output terminal of the boost converter;

an in-rush current flows into the bulk capacitor for a predetermined transient period following initial application of power to the ballast, the in-rush current having a peak value;

the boost converter supplies a high frequency current to the bulk capacitor during steady-state operation of the ballast; and

the passive in-rush current reduction circuit includes;

a transient mode wherein, following initial application of power to the ballast, a substantial portion of the in-rush current flows through the in-rush current limiting resistor, thereby effecting a reduction in the peak value of the in-rush current; and

a steady-state mode wherein a substantial portion of the high frequency current supplied to the bulk capacitor by the boost converter flows through the bypass capacitor, thereby effecting a reduction in the steady-state power dissipated in the in-rush current limiting resistor; and

an inverter that is coupled across the output terminals of the boost converter, the inverter being adapted to light at least one fluorescent lamp.

11. The electronic ballast of claim 10, wherein the in-rush current reduction circuit includes a bypass diode connected in parallel with the in-rush current limiting resistor and the bypass capacitor, wherein the bypass diode is oriented to provide a path around the in-rush current limiting resistor for current flowing out of the bulk capacitor.

12. The electronic ballast of claim 10, wherein the boost converter comprises:

a boost inductor connected between a first node and a second node, and the first node is coupled to the first input terminal of the boost converter;

a boost switch connected between the second node and a third node, and the third node is coupled to the second input terminal of the boost converter and the second output terminal of the boost converter;

a boost rectifier connected between the second node and a fourth node, and the fourth node is coupled to the first output terminal of the boost converter; and

a control circuit for driving the boost switch.

13. The electronic ballast of claim 10, wherein the rectifying circuit comprises a full-wave diode bridge.

14. The electronic ballast of claim 10, wherein the bypass capacitor has a predetermined capacitance to provide a low impedance path around the in-rush current limiting resistor for high frequency current flowing into the bulk capacitance.

15. The electronic ballast of claim 14, wherein the resistance of the in-rush current limiting resistor is in the range of about 0.1 ohm to about ten thousand ohms, and the capacitance of the bypass capacitor is in the range of about 0.1 microfarad to about 10 microfarads.

16. An electronic ballast for powering gas discharge lamps, comprising:

a rectifying circuit having a pair of input terminals for receiving a source of alternating current and having a pair of output terminals, wherein the rectifying circuit comprises a full-wave diode bridge;

a boost converter having a pair of input terminals and having a pair of output terminals, the input terminals of the boost converter being coupled to the output terminals of the rectifying circuit, wherein the boost converter comprises;

a boost inductor connected between a first node and a second node, wherein the first node is coupled to a first input terminal of the boost converter;

a boost switch connected between the second node and a third node, wherein the third node is coupled to a second input terminal of the boost converter and a second output terminal of the boost converter;

a boost rectifier connected between the second node and a fourth node, wherein the fourth node is coupled to a first output terminal of the boost converter; and

a control circuit for driving the boost switch; and

a series circuit that is coupled across the output terminals of the boost converter and that includes a passive in-rush current reduction circuit and a bulk capacitor, the passive in-rush current reduction circuit comprising an in-rush current limiting resistor and a bypass capacitor connected in parallel with each other, wherein;

the in-rush current limiting resistor and the bypass capacitor are coupled between the bulk capacitor and the first output terminal of the boost converter;

the bulk capacitator is coupled between the in-rush current reduction circuit and the second output terminal of the boost converter;

an in-rush current flows into the bulk capacitor for a predetermined transient period following initial application of power to the ballast, the in-rush current having a peak value;

the boost converter supplies a high frequency current to the bulk capacitor during steady-state operation of the ballast; and

the passive in-rush current reduction circuit includes;

a transient mode wherein, following initial application of power to the ballast, a substantial portion of the in-rush current flows through the in-rush current limiting resistor, thereby effecting a reduction in the peak value of the in-rush current; and

a steady-state mode wherein a substantial portion of the high frequency current supplied to the bulk capacitor by the boost converter flows through the bypass capacitor, thereby effecting a reduction in the steady-state power dissipated in the in-rush current limiting resistor; and

an inverter that is coupled across the output terminals of the boost converter, the inverter being adapted to light at least one fluorescent lamp.

17. The electronic ballast of claim 16, wherein the in-rush current reduction circuit includes a bypass diode connected in parallel with the in-rush current limiting resistor and the bypass capacitor, wherein the bypass diode is oriented to provide a path around the in-rush current limiting resistor for current flowing out of the bulk capacitor.