Amplifier for use in time-sharing applications

• US 5,835,049 A
• Filed: 03/27/1997
• Issued: 11/10/1998
• Est. Priority Date: 03/27/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Nagaraj, Krishnaswamy
• Primary Examiner(s): Williams, Howard L.
• Assistant Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US08/828,977
• Time in Patent Office: 593 Days
• Field of Search: 341/161, 341/155, 330/9, 330/51, 327/52, 327/53, 327/65, 327/389, 327/563, 327/96
• US Class Current: 341/161
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03M 1/0675 using redundancy
• CPC Class Codes: H03M 1/1225 using time-division multiplexing
• CPC Class Codes: H03M 1/442 using switched capacitors

Abstract

A differential amplifier has (at least) four input-stage transistors that are switchably coupled to the inverting and noninverting input terminals and to the output terminal(s). In one embodiment, two of the transistors are permanently coupled between the input and output terminals, while the other two transistors are switchably coupled the input and output terminals, such that, during two-phased operations, each of the switchably coupled transistors is alternately connected in parallel to a different one of the two permanently coupled transistors. In this way, any charge (due to input capacitance) in one input-stage transistor from the previous clock phase will tend to negate similar charge in another input-stage transistor at the start of each clock phase. Such an amplifier can be efficiently used in time-sharing applications. For example, when used as the amplifier shared between two stages of a pipelined analog-to-digital converter, crosstalk between stages otherwise due to input capacitance of the amplifier can be reduced and possibly eliminated.

Claims

1. A differential amplifier having an inverting input terminal and a noninverting input terminal and at least one output terminal, comprising four transistors forming an input stage of the differential amplifier and coupled to the inverting and noninverting input terminals and to the output terminal, such that at least two of the transistors are capable of being switched between the inverting and noninverting input terminals on different phases of a clock signal capable of driving the differential amplifier.

2. The invention of claim 1, wherein the differential amplifier is time-shared between two or more operations.

3. The invention of claim 2, wherein the differential amplifier is time-shared between two stages of a pipelined analog-to-digital (A/D) converter.

4. The invention of claim 1, wherein:

the gates of the first and fourth transistors are permanently coupled to the noninverting and inverting input terminals, respectively; and

the second and third transistors are switchably coupled in parallel with the first and fourth transistors, such that;

when the second transistor is coupled in parallel to the first transistor, the third transistor is coupled in parallel to the fourth transistor; and

when the second transistor is coupled in parallel to the fourth transistor, the third transistor is coupled in parallel to the first transistor.

5. The invention of claim 4, wherein:

the gates of the second and third transistors are switchably coupled to the noninverting and inverting input terminals, such that;

when the gate of the second transistor is coupled to the noninverting input terminal, the gate of the third transistor is coupled to the inverting input terminal; and

when the gate of the second transistor is coupled to the inverting input terminal, the gate of the third transistor is coupled to the noninverting input terminal; and

the drains of the second and fourth transistors are switchably coupled to the drains of the first and fourth transistors, such that;

when the drain of the second transistor is coupled to the drain of the first transistor, the drain of the third transistor is coupled to the drain of the fourth transistor; and

when the drain of the second transistor is coupled to the drain of the fourth transistor, the drain of the third transistor is coupled to the drain of the first transistor.

6. The invention of claim 5, wherein the differential amplifier is time-shared between two or more operations.

7. The invention of claim 6, wherein the differential amplifier is time-shared between two stages of a pipelined A/D converter.

8. An integrated circuit having a differential amplifier comprising an inverting input terminal and a noninverting input terminal and at least one output terminal, the differential amplifier comprising four transistors forming an input stage of the differential amplifier and coupled to the inverting and noninverting input terminals and to the output terminal, such that at least two of the transistors are capable of being switched between the inverting and noninverting input terminals on different phases of a clock signal capable of driving the differential amplifier.

9. The invention of claim 8, wherein the differential amplifier is time-shared between two or more operations.

10. The invention of claim 9, wherein the differential amplifier is time-shared between two stages of a pipelined A/D converter.

11. The invention of claim 8, wherein:

the gates of the first and fourth transistors are permanently coupled to the noninverting and inverting input terminals, respectively; and

the second and third transistors are switchably coupled in parallel with the first and fourth transistors, such that;

when the second transistor is coupled in parallel to the first transistor, the third transistor is coupled in parallel to the fourth transistor; and

when the second transistor is coupled in parallel to the fourth transistor, the third transistor is coupled in parallel to the first transistor.

12. The invention of claim 11, wherein:

the gates of the second and third transistors are switchably coupled to the noninverting and inverting input terminals, such that;

when the gate of the second transistor is coupled to the noninverting input terminal, the gate of the third transistor is coupled to the inverting input terminal; and

when the gate of the second transistor is coupled to the inverting input terminal, the gate of the third transistor is coupled to the noninverting input terminal; and

the drains of the second and fourth transistors are switchably coupled to the drains of the first and fourth transistors, such that;

when the drain of the second transistor is coupled to the drain of the first transistor, the drain of the third transistor is coupled to the drain of the fourth transistor; and

when the drain of the second transistor is coupled to the drain of the fourth transistor, the drain of the third transistor is coupled to the drain of the first transistor.

13. The invention of claim 12, wherein the differential amplifier is time-shared between two or more operations.

14. The invention of claim 13, wherein the differential amplifier is time-shared between two stages of a pipelined A/D converter.