Video refresh compression

• US 5,835,082 A
• Filed: 05/27/1997
• Issued: 11/10/1998
• Est. Priority Date: 12/27/1994
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Perego, Richard E.
• Primary Examiner(s): Saras, Steven J.
• Assistant Examiner(s): WU, XU MING
• Application Number:
  US08/863,123
• Time in Patent Office: 532 Days
• Field of Search: 345/118, 345/119, 345/202, 345/116, 345/507, 345/516, 345/203, 364/232, 364/233
• US Class Current: 345/555
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: G09G 2320/103 Detection of image changes, e.g. determination of an index representative of the image change
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A data compression apparatus and method of displaying graphics in a computer system employs a full frame buffer and compressed frame buffer wherein pixel data is sent to a display device and concurrently compressed and captured in parallel so that subsequent unchanged frames are regenerated directly from the compressed frame buffer.

Claims

1. A video refresh compression system comprising:

(a) rendering means for rendering pixel data to form at least one video frame wherein the video frame comprises a plurality of display data elements and each display data element comprises a plurality of pixel data, and wherein each of the plurality of display data elements are independently compressible with respect to each other;

(b) a full frame buffer having an input coupled to receive and store the pixel data from the rendering means and an output for providing uncompressed display data elements;

(c) a compressed frame buffer to store compressed display data elements having an input and an output;

(d) a data compressor having an input coupled to the output from the full frame buffer to receive and compress display data elements and an output coupled to the input on the compressed frame buffer;

(e) a data decompressor having an input coupled to the output from the compressed frame buffer and an output;

(f) tag means having a plurality of valid bits settable responsive to the data compressor, for validating compressed display data elements stored in the compressed frame buffer;

(g) display control circuitry, coupled and responsive to the tag means, to control sourcing of either uncompressed display data elements from the full frame buffer or compressed display data elements from the compressed frame buffer; and

,

(h) a multiplexer having a first input coupled to the output from the full frame buffer, a second input coupled to the output from the data decompressor, a control input coupled to the display control circuitry, and an output for providing display data elements from the first and second inputs to form the video frame.

2. A system as recited in claim 1 wherein the tag means further comprises a plurality of dirty bits settable responsive to the rendering means, for validating each compressed display data element and the display control circuitry is further responsive to the plurality of dirty bits.

3. A system as recited in claim 1 wherein the display control circuitry, is further coupled to the full frame buffer, to synchronize refresh of pixel data from the rendering means.

4. A system as recited in claim 3 further comprising (i) programmable frame rate control means, coupled to the display control circuitry and the tag means, for programming a rate that the plurality of dirty bits are qualified.

5. A system as recited in claim 1 wherein the full and compressed frame buffers reside in a unified memory.

6. A system as recited in claim 5 wherein the unified memory further comprises main memory.

7. A system as recited in claim 1 wherein the rendering means is a central processing unit.

8. A system as recited in claim 1 wherein the rendering means is a graphics engine.

9. A video refresh compression system comprising:

(a) rendering means for rendering pixel data to form at least one video frame wherein the video frame comprises a plurality of display data elements and each display data element comprises a plurality of pixel data, and wherein each of the plurality of display data elements are independently compressible with respect to each other;

(b) full frame buffer means, coupled to receive pixel data from the rendering means, for buffering and sourcing uncompressed display data elements;

(c) compressed frame buffer means for buffering compressed display data elements;

(d) data compressor means, coupled between the full frame buffer means and the compressed frame buffer means, for compressing the display data elements as the display data elements are sourced from the full frame buffer means and storing the display data elements in the compressed frame buffer means;

(e) data decompressor means, coupled to the compressed frame buffer means, for decompressing the display data elements;

(f) valid tag means, responsive to the data compressor means and including a valid bit for each compressed data element, for maintaining coherency between the full frame buffer means and the compressed frame buffer means;

(g) display control means, coupled and responsive to the valid tag means, for controlling whether each display data element is sourced from either the full frame buffer means or the compressed frame buffer means; and

,

(h) multiplexer means, coupled to the full frame buffer means, the data compressor means, and the display control means, for outputting display data elements to form the video frame.

10. A system as recited in claim 9 wherein the valid tag means further comprises a dirty bit for each compressed display data element and wherein the dirty bit is controlled by the rendering means and the valid bit is controlled by the data compressor means.

11. A system as recited in claim 9 wherein the display control means is further coupled to the full frame buffer means, for synchronizing refresh of pixel data from the rendering means.

12. A system as recited in claim 11 further comprising (i) programmable frame rate control means, coupled to the display control means and the valid tag means, for programming a rate that the dirty bits are qualified.

13. A system as recited in claim 9 wherein the full and compressed frame buffer means reside in a unified memory.

14. A system as recited in claim 13 wherein the unified memory further comprises main memory.

15. A video refresh method wherein a video frame comprises a plurality of display data elements and each display data element comprises a plurality of pixel data, and wherein each of the plurality of display data elements are independently compressible with respect to each other, comprising the steps of:

(a) rendering pixel data to a full frame buffer;

(b) in response to display control circuitry, sending uncompressed display data elements from the full frame buffer to a display device;

(c) concurrently compressing the uncompressed display data elements as it is sent to the display device and storing the compressed display data elements in a compressed frame buffer;

(d) validating a plurality of valid bits corresponding to the plurality of compressed display data elements compressed in step (c);

(e) on subsequent updates by the display control circuitry, decompressing the compressed display data elements in the compressed frame buffer for each of the compressed display data elements having corresponding valid bits set valid; and

,

(f) sending to the display device the display data elements decompressed in step (e) and otherwise sending uncompressed display data elements from the full frame buffer as in step (b) to form a video frame.

16. A method as recited in claim 15 further comprising the step of (g) setting a dirty bit in a plurality of dirty bits as the pixel data is rendered to the full frame buffer in step (a).

17. A method as recited in claim 16 further comprising the step of (h) qualifying the plurality of dirty bits at a rate slower than a rate of sending the uncompressed display data elements from the full frame buffer to a display device in step (b).

18. A method as recited in claim 17 wherein step (f) further comprises a condition that the dirty bit is not set or not qualified.

19. A video refresh method wherein a video frame comprises a plurality of display data elements and each display data element comprises a plurality of pixel data, and wherein each of the plurality of display data elements are independently compressible with respect to each other, comprising steps of:

(a) associating a first tag and a second tag with each of the plurality of display data elements of the video frame;

(b) updating a display data element in a full frame buffer from a source of pixel data and setting the first tag of the display data element;

(c) clearing the first tag and the second tag associated with a display data element when that display data element is output from the full frame buffer, and for each display data element that is compressible, compressing and storing the compressed display data element in a compressed frame buffer and setting the associated second tag as each display data element that is compressible is output from the full frame buffer;

(d) outputting a display data element from the full frame buffer for video frame refresh if the associated first tag is set and the associated second tag is cleared; and

,

(e) outputting and decompressing a display data element from the compressed frame buffer for video frame refresh if the associated first tag is not set and the associated second tag is set.

20. A method as recited in claim 19 further comprising the step of qualifying display data elements every Nth frame wherein N is a number of frames and wherein step (e) is further conditioned on the associated first tag being not qualified.

21. A computer system comprising:

(a) a display for displaying video frames wherein each video frame comprises a plurality of display data elements and each display data element comprises a plurality of pixel data, and wherein each of the plurality of display data elements are independently compressible with respect to each;

(b) a processor that provides pixel data;

(c) a full frame buffer to store uncompressed display data elements having an input coupled to the processor to receive and store the pixel data and an output for providing the uncompressed display data elements;

(d) a compressed frame buffer to store compressed display data elements having an input and an output;

(e) a data compressor to compress display data elements having an input coupled to the output from the full frame buffer to receive and compress display data elements and an output coupled to the input on the compressed frame buffer;

(f) a data decompressor having an input coupled to the output from the compressed frame buffer and an output;

(g) a tag memory having a plurality of valid bits settable responsive to the data compressor, for validating each compressed display data element stored in the compressed frame buffer;

(h) display control circuitry, coupled and responsive to the tag memory, to control sourcing of either uncompressed display data elements from the full frame buffer or compressed display data elements from the compressed frame buffer; and

,

(i) a multiplexer having a first input coupled to the output from the full frame buffer, a second input coupled to the output from the data decompressor, a control input coupled to the display control circuitry, and an output responsive to the display control circuitry, for providing display data elements from the first and second inputs to form the video frame.

22. In a computer system having a display and a processor, a method of refreshing a video frame displayed on the display wherein the video frame comprises a plurality of display data elements and each display data element comprises a plurality of pixel data, and each of the plurality of display data elements are independently compressible with respect to each other, comprising steps of:

(a) providing pixel data from the processor to a full frame buffer;

(b) in response to display control circuitry, sending uncompressed display data elements from the full frame buffer to the display;

(c) compressing the uncompressed display data elements as it is sent to the display and storing the compressed display data elements in a compressed frame buffer;

(d) validating a plurality of valid bits corresponding to a plurality of compressed display data elements compressed in step (c); and

,

(e) so long as the valid bit corresponding to each compressed display data element is valid, on subsequent updates by the display control circuitry, decompressing the compressed display data elements in the compressed frame buffer and sending it to the display and otherwise sending uncompressed display data elements from the full frame buffer to refresh the video frame on the display.

23. A computer system comprising:

(a) a display;

(b) a processor that provides pixel data to form a video frame wherein the video frame comprises a plurality of display data elements and each display data element comprises a plurality of pixel data, and wherein each of the plurality of display data elements are independently compressible with respect to each other;

(c) a unified memory coupled to the processor and having an input and an output and including;

(i) a full frame buffer to store uncompressed display data elements; and

(ii) a compressed frame buffer to store compressed display data elements;

(d) a data compressor having an input coupled to the full frame buffer and an output coupled to the compressed frame buffer, to concurrently compress uncompressed display data elements as the uncompressed display data elements are sourced by the full frame buffer;

(e) a data decompressor having an input coupled to the output from the unified memory and an output to decompress compressed display data elements;

(f) a tag memory having a plurality of valid bits for validating each compressed display data element stored in the compressed frame buffer;

(g) display control circuitry coupled and responsive to the tag memory, to control sourcing of either uncompressed display data elements from the full frame buffer or compressed display data elements from the compressed frame buffer; and

,

(h) a multiplexer having a first input coupled to the unified memory, a second input coupled to the output from the data decompressor, a control input coupled to the display control circuitry, and an output responsive to the display control circuitry, for providing display data elements to the display to refresh each video frame from the first and second inputs of the multiplexer.

24. In a computer system having a display, a processor, and unified memory, a method of refreshing each video frame on the display comprising steps of:

(a) providing pixel data from the processor to a full frame buffer residing in unified memory to form video frames wherein each video frame comprises a plurality of display data elements and each display data element comprises a plurality of pixel data, and wherein each of the plurality of display data elements are independently compressible with respect to each other;

(b) in response to display control circuitry, sending uncompressed display data elements from the full frame buffer to the display;

(c) compressing the uncompressed display data elements when the uncompressed display data elements are sent to the display and storing the compressed display data elements in a compressed frame buffer residing in unified memory;

(d) validating a plurality of valid bits corresponding to the compressed display data elements compressed in step (c); and

,

(e) so long as the valid bit corresponding to each compressed display data element is valid, on subsequent updates by the display control circuitry, decompressing the compressed display data elements in the compressed frame buffer and sending it to the display and otherwise sending uncompressed display data elements from the full frame buffer to refresh the video frame on the display.