System for transmission and recovery of digital data using video graphics display processor and method of operation thereof

• US 5,835,102 A
• Filed: 10/19/1995
• Issued: 11/10/1998
• Est. Priority Date: 10/19/1995
• Status: Expired due to Fees

• Current Assignee: SPARTA, Inc. (New Port Group Holdings, Inc.)
• Original Assignee: SPARTA, Inc. (New Port Group Holdings, Inc.)
• Inventors: Monroe, John W. III, Smith, John J., Kenyon, Stephen C., Anderson, Michael E.
• Primary Examiner(s): Luu, Matthew
• Application Number:
  US08/545,508
• Time in Patent Office: 1,118 Days
• Field of Search: 395/501, 395/507, 395/508, 345/201, 345/185, 345/203, 345/507, 345/508
• US Class Current: 345/545
• CPC Class Codes: G06F 11/1456 Hardware arrangements for backup
• CPC Class Codes: G06F 11/1469 Backup restoration techniques

Abstract

A system (30) for outputting digital data stored in a memory of a computer (12) in accordance with the invention includes a graphics display processor (20), coupled to the memory, for processing the digital data stored in the memory to produce at least one serial data stream including clock information, which is a function of a clock signal representative of a rate at which the at least one display formatted serial data stream is outputted, and display information for use in controlling a video monitor; a video channel (24), coupled to the display processor, for outputting the at least one serial data stream produced by the graphics display processor; a data processing memory (52); and a data processing system (40, 44 and 50) for processing the at least one serial data stream in response to the clock information and for removing at least the display information and controlling storing of the at least one of the at least one serial data stream with the display information removed which contains the digital data read from the memory of the computer system.

Claims

1. A process for outputting digital data stored in a memory of a computer having a graphics display processor comprising:

reading digital data from the memory and processing the digital data to produce at least one serial data stream with the at least one serial data stream including the digital data and clock information, the clock information being a function of a clock signal representative of a rate at which the at least one serial data stream is outputted by a video channel;

serially outputting the at least one formatted serial data stream on the video channel under control of the graphics processor;

at least one of the at least one serial data stream also includes display information which permits the at least one serial data stream to be displayed by a video monitor connectable to the video channel;

processing at least one of the at least one serial data stream after outputting by the video channel to remove the display information from the processed at least one serial data stream; and

producing the clock signal representative of a bit rate at which the at least one serial data stream is outputted by the video channel in response to the clock information in the one of the at least one serial data stream.

2. A process in accordance with claim 1 wherein:

one of the at least one serial data stream contains the clock signal and the display information and another of the at least one serial data stream contains the digital data and the display information.

3. A process in accordance with claim 1 wherein:

one of the at least one serial data stream includes the digital data with at least a portion of the one of the at least one serial data stream being encoded with self-clocking information which permits the clock signal representative of a rate at which the one of the at least one serial data stream is outputted by the video channel to be derived from processing at least the portion of the one of the at least one serial data stream outputted from the video channel.

4. A process in accordance with claim 3 further comprising:

processing the one of the at least one serial data stream to remove the self-clocking information.

5. A process in accordance with claim 4 further comprising:

the processing the one of the at least one serial data stream to remove the self-clocking information includes converting the one of the at least one serial data stream into parallel digital data having a number of bits corresponding to a number of bits stored at each addressable location of the memory from which the digital data was read.

6. A process in accordance with claim 3 wherein:

the at least one serial data stream is outputted in frames formatted for video display, each frame having a set number of lines with each line having bits disposed between periodically occurring horizontal synchronization information with at least a group of bits in each line being encoded with the self-clocking information;

the frames are outputted under control of the graphics display processor on the video channel and stored in another memory; and

the frames stored in the another memory are read out from the another memory in response to detection of storing the set number of lines in the another memory.

7. A process in accordance with claim 4 further comprising:

the at least one serial data stream is outputted in frames formatted for video display, each frame having a set number of lines with each line having bits disposed between periodically occurring horizontal synchronization information with at least a group of bits in each line being encoded with the self-clocking information;

the frames are outputted under control of the graphics display processor on the video channel and stored in another memory; and

the frames stored in the another memory are read out from the another memory in response to detection of storing the set number of lines in the another memory.

8. A process in accordance with claim 5 further comprising:

the at least one formatted serial data stream is outputted in frames formatted for video display, each frame having a set number of lines with each line having bits disposed between periodically occurring horizontal synchronization information with at least a group of bits in each line being encoded with the self-clocking information;

the frames are outputted under control of the graphics display processor on the video channel and stored in another memory; and

the frames stored in the another memory are read out from the another memory in response to detection of storing the set number of lines in the another memory.

9. A process in accordance with claim 6 wherein:

each frame is being stored in one of a first and a second frame buffer of the another memory while another frame is being read out of another of the first and second frame buffer with sequential frames stored in the another memory being read out alternatively from the first and second frame buffers during storing of sequential frames outputted on the video channel.

10. A process in accordance with claim 7 wherein:

each frame is being stored in one of a first and a second frame buffer of the another memory while another frame is being read out of another of the first and second frame buffer with sequential frames stored in the another memory being read out alternatively from the first and second frame buffers during storing of sequential frames outputted on the video channel.

11. A process in accordance with claim 8 wherein:

each frame is being stored in one of a first and a second frame buffer of the another memory while another frame is being read out of another of the first and second frame buffer with sequential frames stored in the another memory being read out alternatively from the first and second frame buffers during storing of sequential frames outputted on the video channel.

12. A process in accordance with claim 6 further comprising:

the frames read out from the another memory in response to detection of the storing of the set number of lines in the another memory are stored in a memory of a processing system in response to an interrupt signal produced in response to the detection of the storing of set number of lines in the another memory.

13. A process in accordance with claim 7 further comprising:

the frames read out from the another memory in response to detection of the storing of the set number of lines in the another memory are stored in a memory of a processing system in response to an interrupt signal produced in response to the detection of the storing of set number of lines in the another memory.

14. A process in accordance with claim 8 further comprising:

the frames read out from the another memory in response to detection of the storing of the set number of lines in the another memory are stored in a memory of a processing system in response to an interrupt signal produced in response to the detection of the storing of set number of lines in the another memory.

15. A process in accordance with claim 9 further comprising:

the frames read out from the another memory in response to detection of the storing of the set number of lines in the another memory are stored in a memory of a processing system in response to an interrupt signal produced in response to the detection of the storing of set number of lines in the another memory.

16. A process in accordance with claim 10 further comprising:

the frames read out from the another memory in response to detection of the storing of the set number of lines in the another memory are stored in a memory of a processing system in response to an interrupt signal produced in response to the detection of the storing of set number of lines in the another memory.

17. A process in accordance with claim 11 further comprising:

the frames read out from the another memory in response to detection of the storing of the set number of lines in the another memory are stored in a memory of a processing system in response to an interrupt signal produced in response to the detection of the storing of set number of lines in the another memory.

18. A process in accordance with claim 4 wherein the one serial data stream comprises:

a sequence of frames with each frame being serially read out as a series of lines under control of the graphics display processor;

each frame is processed to remove the self-clocking information while retaining the digital data;

the processed frames are stored in a backup memory; and

the frames stored in the backup memory are read back into the memory of the computer to restore the digital data originally stored in the memory of the computer.

19. A system for outputting digital data stored in a memory of a computer comprising:

a graphics display processor, coupled to the memory, for processing the digital data stored in the memory to produce at least one serial data stream including clock information, which is a function of a clock signal representative of a rate at which the at least one display formatted serial data stream is outputted, and display information for use in controlling a video monitor;

a video channel, coupled to the graphics display processor, for outputting the at least one serial data stream produced by the graphics display processor;

a data processing memory; and

a data processing system, coupled to the video channel and to the data processing memory, for processing the at least one serial data stream in response to the clock information and for removing at least the display information and controlling storing of the at least one of the at least one serial data stream with the display information removed in the data processing memory which contains the digital data read from the memory of the computer system.

20. A system in accordance with claim 19 wherein:

one of the at least one serial data stream contains the clock signal and display information and another of the at least one serial data stream contains the digital data and the display information.

21. A system in accordance with claim 19 wherein:

one of the at least one serial data stream includes the digital data with at least a portion of the one of the at least one serial data stream being encoded with self-clocking information which permits the clock signal representative of a rate at which the one of the at least one serial data stream is outputted by the video channel to be derived from processing the portion of the one of the at least one serial data stream outputted from the video channel.

22. A system in accordance with claim 21 further comprising:

a storage processor memory; and

a storage processor, coupled to the data processing system and to the storage processor memory, for controlling storing of data read out from the data processing memory in the storage processor memory in response to the data processor memory storing a data block of a set size.

23. A system in accordance with claim 22 wherein:

the set size is a full frame of information formatted by the graphics display processor for display by the video monitor.

24. A system in accordance with claim 23 wherein the at least one serial data stream encoded with self-clocking information comprises:

frames having a set number of lines and bits disposed between periodically occurring horizontal synchronization information with at least a group of bits in each line being encoded with the self-clocking information.

25. A system in accordance with claim 24 wherein:

each line is formatted into a packet including a sync field for use in detecting the clock signal and a data field containing data from the digital data stored in the memory of the computer; and

the data processing system comprises a clock, responsive to the sync field, for producing the clock signal and a data separator, responsive to the clock signal and to the lines, for removing the self-clocking information and converting the lines into parallel digital data having a number of bits equal to a number of bits stored at each addressable location of the memory of the computer.

26. A system in accordance with claim 25 wherein:

each packet further includes a scan line field for encoding an address of each line within each frame and a trigger bit field for encoding a number of a frame within a sequence of frames outputted by the video channel; and

each frame is outputted with a vertical synchronization pulse transmitted with each frame and a horizontal synchronization pulse transmitted with each line.

27. A system in accordance with claim 26 wherein the data processing memory comprises:

first and second frame buffers; and

wherein

when the trigger field changes in magnitude by one indicating storing of a complete frame from one of the sequence of frames in one of the frame buffers of the data processing memory, the data processing system causes the complete frame to be read out from the one of the first and second frame buffers and controls storing of another one of the frames in another of the first and second frame buffers of the data processing memory.

28. A system in accordance with claim 27 wherein:

the data processing system produces an interrupt in response to the change in magnitude of the trigger field by one; and

in response to reception of the interrupt from the data processing system, the storage processor initiates storing of the frame read out from the one of the first and second frame buffers of the data processing memory in the storage processor memory.

29. A system in accordance with claim 28 wherein the storage processor memory comprises:

first and second frame buffers, each storage processor frame buffer storing a frame in response to the reception of the interrupt from the data processing system with the storage processor first and second frame buffers alternatively storing and outputting a frame.

30. A system in accordance with claim 29 wherein:

the storage processor memory is a backup memory and the storage processor writes frames stored in the storage processor memory back into the memory of the computer to restore the original digital data.

38. A process in accordance with claim 27 wherein:

the memory of the processing system has first and second processing system frame buffers and the first and second processing system frame buffers store a sequence of frames in response to the interrupt to cause each of the first and second processing system frame buffers to alternatively store a frame.

31. A system for backing up digital data stored in a memory of a computer comprising:

a graphics display processor, coupled to the memory, for processing the digital data stored in the memory to produce at least one serial data stream including the digital data and clock information which is a function of a clock signal representative of a rate at which the at least one serial data stream is outputted;

a video channel, coupled to the display processor, for outputting the at least one serial data stream produced by the graphics display processor; and

a back up memory, coupled to the video channel, in which is written the at least one serial data stream from the video channel in a word format and provides the written digital data back to the memory to restore the digital data in the memory of the computer.

32. A system in accordance with claim 31 wherein the clock information comprises:

at least a portion of one of the at least one serial data stream encoded with self-clocking information which permits the clock signal to be derived from processing at least the portion of one of the at least one serial data stream.

33. A system in accordance with claim 31 wherein the at least one serial data stream further comprises:

display information for use in controlling a video monitor and the system further including a subsystem, coupled to the at least one serial data stream and the memory, for processing the at least one serial data stream to remove the display information, to reformat the at least one digital data stream into the word format having a format identical to a word format in which the digital data is stored in the memory and for forwarding the words to the backup memory for storage therein.

34. A process for outputting digital data stored in a memory of a computer having a graphics display processor comprising:

reading digital data from the memory and processing the digital data to produce at least one serial data stream with the at least one serial data stream including the digital data and clock information, the clock information being a function of a clock signal representative of a rate at which the at least one serial data stream is outputted by a video channel;

serially outputting the at least one formatted serial data stream on the video channel under control of the graphics processor; and

wherein

at least one of the at least one serial data stream comprises a sequence of frames with each frame being serially read out as a series of lines under control of the graphics display processor, each line being formatted into a packet including the clock information comprising a sync field used for producing the clock signal, a scan line field for encoding an address of each line within each frame, a trigger field for encoding a number of a frame within the sequence of frames being outputted on the video channel, and a data field containing data from the block of digital data; and

wherein

each frame is transmitted with a vertical synchronization pulse and a horizonal synchronization pulse is transmitted with each line.

35. A process in accordance with claim 34 wherein:

the sync field is processed to produce the clock signal; and

the sequence of frames are processed with the clock signal to remove the clock information and to convert each packet into parallel information formatted into groups of bits with each group of bits being equal in number to a number of bits stored at each addressable location in the memory from which the block of digital data was read.

36. A process in accordance with claim 35 wherein:

the sequence of frames is stored in another memory having first and second frame buffers; and

when the trigger field changes in magnitude by one indicating storing of a complete frame from one of the sequence of frames in one of the frame buffers of the another memory the complete frame is read out from the one of the first and second frame buffers and storing of a subsequent one of the frames is begun in another of the first and second frame buffers while the complete frame is being read out.

37. A process in accordance with claim 36 wherein:

an interrupt is produced in response to the change in magnitude of the trigger field by one; and

the interrupt is received by a processing system which initiates storing of the frame read out from the one of the first and second frame buffers in response to the interrupt in a memory of the processor system.

39. A process for outputting digital data stored in a memory of a computer having a graphics display processor comprising:

reading digital data, without clock information, from the memory and processing the digital data to produce at least one serial data stream with the at least one serial data stream including the digital data and clock information, the clock information being a function of a rate at which the at least one serial data stream is outputted by a video channel and not being synchronization information used for controlling display of information from the video channel; and

serially outputting the at least one serial data stream on the video channel under control of the graphics processor.

40. A process in accordance with claim 39 wherein:

the clock information is encoded into the digital data after reading of the digital data from the memory; and

the clock information is used for processing the serial data stream to store the digital data in a word format in another memory.

41. A process in accordance with claim 39 wherein:

the clock information comprises another serial data stream separate from the digital data stream; and

the clock information is used for processing the serial data stream to store the digital data in a word format in another memory.

42. A process in accordance with claim 40 wherein:

the word format is identical to a word format used to store the digital data in the memory; and

reading the data stored in the another memory to restore the digital data stored in the memory.

43. A process in accordance with claim 41 wherein:

the word format is identical to a word format used to store the digital data in the memory; and

reading the data stored in the another memory to restore the digital data stored in the memory.