Three-dimensional read-only memory

• US 5,835,396 A
• Filed: 10/17/1996
• Issued: 11/10/1998
• Est. Priority Date: 10/17/1996
• Status: Expired due to Term

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US08/732,902
• Time in Patent Office: 754 Days
• Field of Search: 365/51, 365/63, 365/94, 365/96
• US Class Current: 365/51
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 27/1021 including diodes only

Abstract

A read-only memory structure, having a three dimensional arrangement of memory elements, is disclosed. The memory elements are partitioned into multiple memory levels. Each memory level is stacked on top of another. Within each memory level, there are a plurarity of memory elements and address select lines. The memory elements can be either mask programmable or electrical programmable.

Claims

1. A read-only memory element in an integrated circuit comprising:

a first electrode, said first electrode comprising metallic materials;

a second electrode, said second electrode comprising metallic materials;

a quasi-conduction layer separating said first electrode and said second electrode, said quasi-conduction layer being a nonlinear resistor, having a low resistance at the read voltage and having a higher resistance when the applied voltage is smaller than the read voltage.

2. The read-only memory element according to claim 1 wherein said quasi-conduction layer comprises a semiconductor material.

3. The read-only memory element according to claim 1 wherein said semiconductor material is selected from the group of C, Si, Ge, Sn, SiC, GaAs.

4. The read-only memory element according to claim 1 wherein said semiconductor material is doped.

5. The read-only memory element according to claim 1 wherein said quasi-conduction layer has a higher resistance when the polarity of the applied voltage is opposite to the polarity of the read voltage.

6. The read-only memory element according to claim 5 wherein said quasi-conduction layer further comprises a first semiconductor layer and a second semiconductor layer, said first semiconductor layer and said second semiconductor layer being opposite doped.

7. The read-only memory element according to claim 1 wherein said quasi-conduction layer has a non-single-crystalline structure.

8. The read-only memory element according to claim 1 further comprising an antifuse layer between said first electrode and said second electrode, said antifuse layer being non-conductive when said antifuse layer is unprogrammed, said antifuse layer being conductive when said antifuse layer is programmed.

9. The read-only memory element according to claim 8 further comprising a buffer layer separating said antifuse layer and said quasi-conduction layer, said buffer layer comprising metallic materials.

10. The read-only memory element according to claim 8 wherein said antifuse layer comprises amorphous silicon.

11. The read-only memory element according to claim 8 wherein said antifuse layer comprises protective ceramic materials.

12. A semiconductor integrated circuit having at least one read-only memory level stacked level by level above a semiconductor substrate with decoders thereon, each memory level comprising:

a plurality of spaced-apart memory element select lines, said select lines comprising metallic materials;

a plurality of read-only memory elements, each of said memory elements comprising first and second metallic electrodes, said first metallic electrode being coupled to a first select line, said second metallic electrode being coupled to a second select line;

an interlevel insulating layer covering said select lines and said memory elements at said memory level;

a plurality of interlevel connecting vias through said memory level, said interlevel connecting vias providing coupling means between one memory level and said semiconductor substrate.

13. The semiconductor integrated circuit according to claim 12 wherein at least one of said memory elements further includes a quasi-conduction layer separating said first electrode and said second electrode, said quasi-conduction layer being a nonlinear resistor, having a low resistance at the read voltage and having a higher resistance when the applied voltage is smaller than the read voltage.

14. The semiconductor integrated circuit according to claim 12 wherein at least one of said memory elements further include an antifuse layer separating said first electrode and said second electrode, said antifuse layer being non-conductive when said antifuse layer is unprogrammed, said antifuse layer being conductive when said antifuse layer is programmed.

15. The semiconductor integrated circuit according to claim 12 wherein:

said memory level further comprise a plurality of word lines and a plurality of first contact vias, said word lines being coupled to said semiconductor substrate through said first contact vias;

said semiconductor substrate further comprises a plurality of first contact points for said memory level, said first contact vias making contact with said semiconductor substrate at said first contact points; and

said first contact points form at least one straight line.

16. The semiconductor integrated circuit according to claim 12 wherein:

said memory level further comprise a plurality of bit lines and a plurality of second contact vias, said bit lines being coupled to said semiconductor substrate through said second contact vias;

said semiconductor substrate further comprises a plurality of second contact points for said memory level, said second contact vias making contact with said semiconductor substrate at said second contact points; and

said second contact points form at least one straight line.

17. The semiconductor integrated circuit according to claim 12 wherein the total number of memory levels is greater than or equal to two and said memory levels further include:

a first memory level, said first memory level including a first word line and a first bit line, said first memory level being coupled to a first decoder on said substrate;

a second memory level, said second memory level including a second word line and a second bit line, said second first memory level being coupled to a second decoder on said substrate.

18. The semiconductor integrated circuit according to claim 17 further including at least one routing level, whereby said first decoder is spaced away from said second decoder.

19. The semiconductor integrated circuit according to claim 17 wherein said first word line is connected in series with said second word line.

20. The semiconductor integrated circuit according to claim 17 wherein said first bit line is connected in series with said second bit line.