Method and mechanism for checking integrity of byte enable signals
First Claim
1. A parity fault detection system comprising:
- a parity generator configured to generate a parity bit wherein said parity bit is an even parity bit or an odd parity bit in dependence on the state of a control signal; and
a parity checker configured to check said parity bit for even parity or odd parity depending on the state of said control signal, wherein said parity checker includes;
a first parity tree with a plurality of inputs and an output;
a first inverter with an input coupled to said output of said first parity tree, and an output;
a first multiplexer with one input coupled to said output of said first parity tree, one input coupled to said output of said first inverter, a select input coupled to said control signal, and an output; and
an exclusive-or gate coupled to said first multiplexer output and said parity bit.
1 Assignment
0 Petitions
Accused Products
Abstract
A device and method that enables fault detection of control lines without additional fault detection lines. Prior to the transfer of a group of data, a control line is used to select whether even or odd parity is used on the group of data. After the data transfer, the same control signal is used at the destination device to select the type of parity used to check the validity of the data. If an error occurs on the control line that causes the state of the control line to change, the destination device will use the a different type of parity (even or odd parity) to check the validity of the group of data, and an error will be detected. In this manner, an error on the control line can be detected without additional parity signals.
21 Citations
17 Claims
-
1. A parity fault detection system comprising:
-
a parity generator configured to generate a parity bit wherein said parity bit is an even parity bit or an odd parity bit in dependence on the state of a control signal; and a parity checker configured to check said parity bit for even parity or odd parity depending on the state of said control signal, wherein said parity checker includes; a first parity tree with a plurality of inputs and an output; a first inverter with an input coupled to said output of said first parity tree, and an output; a first multiplexer with one input coupled to said output of said first parity tree, one input coupled to said output of said first inverter, a select input coupled to said control signal, and an output; and an exclusive-or gate coupled to said first multiplexer output and said parity bit. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A computer system comprising:
-
a processor core; a memory; a data bus coupled to said processor core and said memory; a control bus coupled to said processor core and said memory; a parity generator coupled to said data bus and said control bus, wherein said parity generator is configured to generate a first parity signal with even parity or odd parity in dependence on the state of a control signal asserted by said processor core on said control bus; and a parity checker coupled to said data bus, said control bus, and coupled to receive said first parity signal, wherein said parity checker checks said first parity signal in dependence on the state of said control signal, wherein said parity checker includes; a first parity tree with a plurality of inputs coupled to said data bus, and an output; an first inverter with an input coupled to said output of said first parity tree, and an output; a first multiplexer with one input coupled to said output of said first parity tree, one input coupled to said output of said first inverter, a select input coupled to receive said control signal from said control bus, and an output; and an exclusive-or gate with one input coupled to said first multiplexer output and one input coupled said first parity signal. - View Dependent Claims (7, 8, 9, 10, 11, 12)
-
-
13. A method of detecting an error on a plurality of data lines and a control line comprising the steps of:
-
generating a first parity signal for a plurality of data bits, wherein said first parity signal is an even parity signal or an odd parity signal depending on the state of a control signal; transferring said plurality of data bits on said plurality of data lines, said control signal on said control line, and said first parity signal to a destination device; said destination device receiving said transferred data bits from said plurality of data lines, said control signal from said control line, and first parity signal; calculating a second parity signal, wherein said second parity signal is an even parity signal or an odd parity signal depending on the state of said received control signal, wherein said calculating a second parity signal comprises; computing a first parity value for said received plurality of data bits; inverting said first parity value; and selecting said first parity value or said inversion of said first parity value as said second parity signal in dependence on said received control signal; and comparing said second parity signal to said received first parity signal. - View Dependent Claims (14, 15, 16, 17)
-
Specification