Data router backup feature

• US 5,835,696 A
• Filed: 11/22/1995
• Issued: 11/10/1998
• Est. Priority Date: 11/22/1995
• Status: Expired due to Term

• Current Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Hess, Gary C.
• Primary Examiner(s): DeCady, Albert
• Application Number:
  US08/561,675
• Time in Patent Office: 1,084 Days
• Field of Search: 395/182.02, 395/183.19, 395/180, 395/181, 395/182.01, 395/182.08, 395/182.09, 395/182.11, 370/16, 370/16.1, 370/216-228, 340/825.01
• US Class Current: 714/10
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: H04L 41/022 Multivendor or multi-standard integration
• CPC Class Codes: H04L 41/06 Management of faults, events, alarms or notifications
• CPC Class Codes: H04L 43/0811 by checking connectivity
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 49/552 by ensuring the integrity of packets received through redundant connections
• CPC Class Codes: H04L 69/40 for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection management of faults, events, alarms or notifications in data switching networks H04L41/06

Abstract

A back-up facility for data routers is enhanced by providing a mutual back-up feature which allows each of the routers to be active at the same time while also providing a standby monitoring function for the other router(s).

Claims

1. A method of providing a backup feature for data processors each having a plurality of input ports for receiving messages from a host processor via respective communications paths, said method comprising the steps of

arranging a first input port of a first data processor and a second input port of a second data processor into a group and respectively designating said first and second input ports as active and standby ports for said group,

responsive to said first port becoming inoperative, causing said second port to assume an identity priorly specified for said first port so that said second port may receive a message that the host transmits to said first port via the respective one of said communications paths for presentation to its associated second data processor, and

arranging said second data processor so that it routes said message to a second input port of said first data processor by inserting a local address associated with said second input port of said first data processor in said message and then outputting said message to said one of said communications paths for receipt by the latter input port, thereby causing said message to be delivered to said first processor as intended.

2. The method of claim 1 further comprising the steps of

arranging said second input port of said first data processor and a first input port of said second data processor into another group and respectively designating those two ports as standby and active for the other group,

responsive to said first input port of said second data processor becoming inoperative, causing said second port of said first data processor to assume an identity priorly specified for said first port of said second data processor so that said second port of said first data processor may receive a message that the host transmits to said first port of said second data processor via another one of said communications paths for presentation to its associated first data processor, and

arranging said first data processor so that it routes said message to the second input port of said second data processor by inserting a local address associated with said second input port of said second data processor and then outputting said message to said other one of said communications paths for receipt by the latter input port, thereby causing said message to be delivered to said second data processor as intended.

3. The method of claim 2 wherein said one of said communications paths and said other one of said communications paths are the same communications path.

4. A method of providing a backup feature for data processors each having a plurality of input ports for receiving messages from a host processor via respective communications paths, said method comprising the steps of

connecting first and second input ports of a first one of said data processors to first and second busses, respectively, said first and second busses connecting to respect data ports of said host,

connecting first and second input ports of a second one of said data processors to said second and first busses, respectively,

causing the first and second input ports of said first and second data processors, respectively, to be active ports and respectively causing the second and first input ports of said first and second data processors to be standby ports such that if the first port of said first data processor becomes inoperable then the first port of said second data processor assumes the active state for said first data processor and such that, alternatively, if the second port of said second data processor becomes inoperable then the second port of said first data processor assumes the active state for said second first data processor.

5. A method of interconnecting data processors each having a plurality of bus interface ports, said method comprising the steps of

connecting a first bus interface port of a first one of said data processors to a bus and connecting a first bus interface port of a second one of said data processor to said bus, and

causing the first bus interface port of said first processor to be an active port so that it removes messages destined for said first data processor from said bus and causing the first bus interface port of said second data processor to be a standby port such that it becomes the active port for said first data processor if the first bus interface port of said first processor becomes inoperable.

6. The method of claim 5 further comprising the steps of

connecting a second bus interface port of said first one of said data processors to another bus and connecting a second bus interface port of said second one of said data processor to said other bus, and

causing the second bus interface port of said second data processor to be an active port so that it removes messages destined for said second data processor from said other bus and causing the second first bus interface port of said first data processor to be a standby port such that it becomes the active port for said second data processor if the second bus interface port of said second data processor becomes inoperable.

7. An architecture for interconnecting data processors each having a plurality of bus interface ports comprising

connecting a first bus interface port of a first one of said data processors to a bus extending to a host processor and connecting a first bus interface port of a second one of said data processors to said bus, and

arranging the first bus interface port of said first data processor so that it operates as an active port and removes messages destined for said first data processor from said bus and arranging the first bus interface port of said second data processor so that it operates as a standby port such that it becomes the active port for said first data processor if the first bus interface port of said first processor becomes inoperable.

8. The architecture of claim 7 further comprising

connecting a second bus interface port of said first data processors to another bus also extending to said host processor and connecting a second bus interface port of said second data processor to said other bus, and

arranging the second bus interface port of said second data processor so that it operates as active port so that it removes messages destined for said first data processor from said other bus and arranging the second bus interface port of said first data processor so that it operates as a standby port such that it becomes the active port for said second data processor if the second bus interface port of said second data processor becomes inoperable.

9. A apparatus for backing up data processors each having a plurality of input ports for receiving messages from a host processor via respective communications paths comprising

connecting a first input port of a first data processor and a second input port of a second data processor into a group and respectively designating said first and second ports as active and standby ports for said group,

means, responsive to said first port becoming inoperative, for causing said second port to assume an identity priorly specified for said first port so that said second port may receive a message that the host transmits to said first port via the respective one of said communications paths for presentation to its associated second data processor, and

means for causing said second data processor to route said message to a second input port of said first data processor so as to cause said message to be delivered to said first processor as intended by said host.