Structure and method for providing reconfigurable emulation circuit

• US 5,835,751 A
• Filed: 07/11/1997
• Issued: 11/10/1998
• Est. Priority Date: 01/31/1992
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Li, Jeong-Tyng, Wang, Ming-Yang, Chen, Nang-Ping, Ko, Robert J., Huang, Thomas B.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Fiul, Dan
• Application Number:
  US08/893,412
• Time in Patent Office: 487 Days
• Field of Search: 395/500, 395/527, 395/551, 395/555, 395/556, 364/488-491, 257/209, 257/529, 326/37, 326/38, 326/39
• US Class Current: 716/117
• CPC Class Codes: A21B 1/245 with a plurality of air nozzles to obtain an impingement effect on the food
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method and a structure provide emulation circuit implemented on a logic block module comprising clocked and unclocked field programmable logic devices (FPGAs). Software modules analyze the target logic circuit and impose delay constraints to require certain storage instances to be implemented on separate FPGAs so as to prevent hold time violation artifacts.

Claims

1. In implementing an emulation circuit from a netlist description of a design, said design receiving a plurality of clock sources, a structure comprising:

means for importing said netlist description into a data structure representing said design;

means for analyzing said data structure to identify, for each storage instance receiving a clock signal in said design, a clock path connecting said clock signal to one of said clock sources from which said clock signal is derived; and

means for implementing a portion of each clock path in a programmable logic device dedicated for clock generation.

2. A structure as in claim 1, further comprising:

means for identifying, for each of said storage instances, data paths starting from either (i) an output data terminal of another storage instance, or (ii) a input terminal of said design, and leading to an input terminal of said storage instance, said data paths including combinatorial circuits;

means for clustering, for each of said storage instance, said storage instance and said data paths in a cluster; and

means for implementing said emulation circuit in a plurality of programmable devices using a method which prefers implementing the data paths and the storage instance of a cluster in the same programmable logic device to implementing said data paths and said storage instance of a cluster in separate programmable logic devices.

3. A structure as in claim 2, further comprising means for constructing a connectivity graph for identifying common signals between a pair of clusters, and wherein said means for implementing said emulation circuit uses a method which prefers implementing a pair of clusters having common signals in the same programmable logic device to implementing a pair of clusters having said common signals in separate programmable devices.

4. A structure as in claim 2, further comprising means for identifying common components between each pair of clusters, and wherein said means for implementing said emulation circuit duplicates, when said clusters are implemented in different programmable devices, said common components in each of said different programmable devices.