Microprocessor with dynamically extendable pipeline stages and a classifying circuit
First Claim
1. A microprocessor comprising:
- a clock input line wherein said clock input line is configured to convey a signal defining a clock cycle;
a plurality of pipeline stages including an execute stage, said execute stage having a first functional circuit adapted to receive an input value wherein said first functional circuit is configured to operate on said input value, and wherein said first functional circuit includes cascaded levels of logic requiring a first time to evaluate instructions of a first group and requiring a second time to evaluate instructions of a second group, said first time being larger than said clock cycle and said second time being smaller than said clock cycle, and wherein said first functional circuit further includes an output line configured to convey an output signal; and
a classifying circuit adapted to receive said input value of said first functional circuit wherein said classifying circuit is configured to generate an operation status, and wherein said operation status provides information indicative of the validity of said output signal for the current clock cycle.
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Abstract
A pipelined microprocessor containing a classifying circuit is provided. The classifying circuit allows an associated pipeline stage to implement a function requiring a larger number of cascaded logic levels than the clock cycle of the microprocessor will allow. The classifying circuit is especially useful with a pipeline stage which implements a "fundamental limit" function (i.e. a function that does not naturally divide into component functions which could be implemented as separate pipeline stages). When an evaluation time larger than a clock cycle is required, the classifying circuit holds the associated pipeline register, thus allowing the circuit to continue uninterrupted with its evaluation. The time interval available for the fundamental limit stage is dynamically extended. Furthermore, in cycles where the fundamental limit function is not required to evaluate, the pipeline operates at a significantly higher clock rate.
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Citations
23 Claims
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1. A microprocessor comprising:
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a clock input line wherein said clock input line is configured to convey a signal defining a clock cycle; a plurality of pipeline stages including an execute stage, said execute stage having a first functional circuit adapted to receive an input value wherein said first functional circuit is configured to operate on said input value, and wherein said first functional circuit includes cascaded levels of logic requiring a first time to evaluate instructions of a first group and requiring a second time to evaluate instructions of a second group, said first time being larger than said clock cycle and said second time being smaller than said clock cycle, and wherein said first functional circuit further includes an output line configured to convey an output signal; and a classifying circuit adapted to receive said input value of said first functional circuit wherein said classifying circuit is configured to generate an operation status, and wherein said operation status provides information indicative of the validity of said output signal for the current clock cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A classifying circuit comprising:
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an input bus; a circuit coupled to said input bus wherein said circuit is configured to operate on an input value conveyed on said input bus, said circuit being further configured to determine whether an associated functional circuit will require more than one cycle to generate an output value from said input value and determine an operation status of said associated functional circuit; an output bus conveying said operation status of said functional circuit. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A method for operating a pipeline stage in a microprocessor, wherein said pipeline stage accepts an input value and performs an operation on said input value and wherein said pipeline stage comprises a classifying circuit which accepts said input value and a pipeline stage register, comprising:
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determining whether said pipeline stage requires more than one cycle to perform said operation on said input value; advancing said pipeline stage in clock cycles wherein said classifying circuit generates a release value; and stalling said pipeline stage in clock cycles wherein said classifying circuit generates a hold value. - View Dependent Claims (23)
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Specification