Microprocessor with dynamically extendable pipeline stages and a classifying circuit

• US 5,835,753 A
• Filed: 04/12/1995
• Issued: 11/10/1998
• Est. Priority Date: 04/12/1995
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Witt, David B.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/421,434
• Time in Patent Office: 1,308 Days
• Field of Search: 395/820, 395/395, 395/551, 395/552, 395/555, 395/556, 395/559
• US Class Current: 713/600
• CPC Class Codes: G06F 7/00 Methods or arrangements for processing data by operating upon the order or content of the data handled logic circuits H03K19/00
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/3873 Variable length pipelines, e.g. elastic pipeline

Abstract

A pipelined microprocessor containing a classifying circuit is provided. The classifying circuit allows an associated pipeline stage to implement a function requiring a larger number of cascaded logic levels than the clock cycle of the microprocessor will allow. The classifying circuit is especially useful with a pipeline stage which implements a "fundamental limit" function (i.e. a function that does not naturally divide into component functions which could be implemented as separate pipeline stages). When an evaluation time larger than a clock cycle is required, the classifying circuit holds the associated pipeline register, thus allowing the circuit to continue uninterrupted with its evaluation. The time interval available for the fundamental limit stage is dynamically extended. Furthermore, in cycles where the fundamental limit function is not required to evaluate, the pipeline operates at a significantly higher clock rate.

Claims

1. A microprocessor comprising:

a clock input line wherein said clock input line is configured to convey a signal defining a clock cycle;

a plurality of pipeline stages including an execute stage, said execute stage having a first functional circuit adapted to receive an input value wherein said first functional circuit is configured to operate on said input value, and wherein said first functional circuit includes cascaded levels of logic requiring a first time to evaluate instructions of a first group and requiring a second time to evaluate instructions of a second group, said first time being larger than said clock cycle and said second time being smaller than said clock cycle, and wherein said first functional circuit further includes an output line configured to convey an output signal; and

a classifying circuit adapted to receive said input value of said first functional circuit wherein said classifying circuit is configured to generate an operation status, and wherein said operation status provides information indicative of the validity of said output signal for the current clock cycle.

2. The microprocessor as recited in claim 1 wherein said operation status generated by said classifying circuit further comprises a hold value, a release value, a valid value, and an invalid value, and wherein said hold value indicates that said first functional circuit has not completed operating on said input value, and wherein said release value indicates that said first functional circuit has completed operating on said input value, and wherein said valid value indicates that said output signal of said first functional circuit is valid, and wherein said invalid value indicates that said output signal of said first functional circuit is invalid.

3. The microprocessor as recited in claim 2 further comprising a first register adapted to provide said input value of said first functional circuit wherein said first register is configured with a hold input line, and wherein said hold input line is coupled to said classifying circuit, and wherein said hold input line is configured to convey a hold signal from said classifying circuit to said register.

4. The microprocessor as recited in claim 3 wherein said hold signal of said first register is configured to be activated when said hold value is generated by said classifying circuit, and wherein said hold signal of said first register is further configured to be deactivated when said release value is generated by said classifying circuit.

5. The microprocessor as recited in claim 3 further comprising a second register wherein said second register is adapted to receive said output of said first functional circuit.

6. The microprocessor as recited in claim 5 wherein said second register is configured with a valid indicator.

7. The microprocessor as recited in claim 6 wherein said valid indicator of said second register is coupled to said classifying circuit such that said classifying circuit provides the value stored within said valid indicator, and wherein said valid indicator stores a valid indication when said classifying circuit generates a valid value, and wherein said valid indicator stores an invalid indication when said classifying circuit generates an invalid value.

8. The microprocessor as recited in claim 5 wherein said register, said second register, and said functional circuit form a pipeline, and wherein said pipeline is advanced according to said clock cycle except when said classifying circuit generates said hold value.

9. The microprocessor of claim 1, further comprising:

a plurality of pipeline stages in series, each said pipeline stage having an input register for providing an incoming signal to said pipeline stage and having an output register for accepting an outgoing signal from said pipeline stage, said input registers and output registers of adjacent ones of said stages being coincident with each other;

one of said pipeline stages being an execute stage, said execute stage containing said first functional circuit and said classifying circuit, said incoming signal of said execute stage being said input value, said outgoing signal of said execute stage being said output signal, said cascaded levels of logic requiring a time to evaluate that is larger than said clock cycle defining a first logic path, said first functional circuit further including cascaded levels of logic requiring a time to evaluate that is smaller than said clock cycle, said cascaded levels of logic requiring a time to evaluate that is smaller than said clock cycle defining a second logic path, said output signal being generated via one of said first and second logic paths.

10. The microprocessor of claim 9, wherein during a clock cycle in which said execute stage output signal is generated via said first logic path, each of said stages subsequent to said execute stage in said series is advanced at the beginning of the next clock cycle and said execute stage and each of said stages prior to said execute stage in said series is stalled at the beginning of the next clock cycle.

11. The microprocessor of claim 10, wherein said execute stage and each of said stages prior to said execute stage in said series is stalled by conveying said operation status generated by said classifying circuit to said input register of said execute stage and each of said stages prior to said execute stage in said series and thereby causing said input registers to retain said incoming signals.

12. The microprocessor of claim 9, wherein during a clock cycle in which said execute stage output signal is generated via said second logic path, each of said stages in said series is advanced at the beginning of the next clock cycle.

13. The microprocessor of claim 1, further comprising a decode stage, a dispatch stage and a writeback stage.

14. The microprocessor of claim 1 wherein said classifying circuit is coupled to said execute stage and configured to stall said execute stage for one clock cycle upon receipt of an instruction of said first group.

15. A classifying circuit comprising:

an input bus;

a circuit coupled to said input bus wherein said circuit is configured to operate on an input value conveyed on said input bus, said circuit being further configured to determine whether an associated functional circuit will require more than one cycle to generate an output value from said input value and determine an operation status of said associated functional circuit;

an output bus conveying said operation status of said functional circuit.

16. The classifying circuit as recited in claim 15 wherein said operation status comprises a hold value and a release value.

17. The classifying circuit as recited in claim 16 wherein said hold value indicates said input should remain constant.

18. The classifying circuit as recited in claim 16 wherein said release value indicates said input is permitted to change.

19. The classifying circuit as recited in claim 15 wherein said operation status comprises a valid value and an invalid value.

20. The classifying circuit as recited in claim 19 wherein said valid value indicates that said associated functional circuit is completing operation on said input.

21. The classifying circuit as recited in claim 20 wherein said invalid value indicates that said associated functional circuit is continuing to operate on said input.

22. A method for operating a pipeline stage in a microprocessor, wherein said pipeline stage accepts an input value and performs an operation on said input value and wherein said pipeline stage comprises a classifying circuit which accepts said input value and a pipeline stage register, comprising:

determining whether said pipeline stage requires more than one cycle to perform said operation on said input value;

advancing said pipeline stage in clock cycles wherein said classifying circuit generates a release value; and

stalling said pipeline stage in clock cycles wherein said classifying circuit generates a hold value.

23. The method as recited in claim 22 further comprising continuing to execute an operation already in progress in a clock cycle following said stalling step.