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Microprocessor with dynamically extendable pipeline stages and a classifying circuit

  • US 5,835,753 A
  • Filed: 04/12/1995
  • Issued: 11/10/1998
  • Est. Priority Date: 04/12/1995
  • Status: Expired due to Term
First Claim
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1. A microprocessor comprising:

  • a clock input line wherein said clock input line is configured to convey a signal defining a clock cycle;

    a plurality of pipeline stages including an execute stage, said execute stage having a first functional circuit adapted to receive an input value wherein said first functional circuit is configured to operate on said input value, and wherein said first functional circuit includes cascaded levels of logic requiring a first time to evaluate instructions of a first group and requiring a second time to evaluate instructions of a second group, said first time being larger than said clock cycle and said second time being smaller than said clock cycle, and wherein said first functional circuit further includes an output line configured to convey an output signal; and

    a classifying circuit adapted to receive said input value of said first functional circuit wherein said classifying circuit is configured to generate an operation status, and wherein said operation status provides information indicative of the validity of said output signal for the current clock cycle.

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