Multiplexed three line synchronous/full-duplex asychronous data bus and method therefor

• US 5,835,785 A
• Filed: 11/14/1994
• Issued: 11/10/1998
• Est. Priority Date: 11/14/1994
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Joglekar, Manohar A., Overtoom, Eric J.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Chen, Anderson I.
• Application Number:
  US08/338,993
• Time in Patent Office: 1,457 Days
• Field of Search: 395/290, 395/285, 395/287, 395/550, 395/309, 370/85.11, 375/219, 375/370, 455/88, 455/73
• US Class Current: 710/14
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A multiplexed synchronous/asynchronous data bus uses three communications lines (T, C, R) to convey bi-directional synchronous data between two data devices at a relatively low data transfer rate. The data bus is configured as a full-duplex asynchronous data bus by communicating a false address between the two data devices on two communications lines (T, C) using the synchronous data bus, holding the two communications lines (T, C) in a logic high state for a period of time, and continuing to hold one of the two communications lines (C) in the logic high state during full-duplex asynchronous communication. Full-duplex asynchronous data can then communicated between the two data devices at a higher data transfer rate on two of the three communications lines (T, R).

Claims

1. A master data device employing a data transmission bus including three communications lines for transmitting a first data message from the master data device to a slave data device at a first rate of data transfer and for transmitting a second data message from the master data device to the slave data device at a second rate of data transfer, each of the two data messages having a plurality of binary bits, each bit having either a binary zero state or a binary one state for a period of time which is related to the data transfer rate, the master data device comprising:

means for applying a first binary state to a first and a second of the three communications lines before and after the first data message;

means for coupling the first data message to the first and second of the three communications lines;

means for coupling a false address of the first data message to the first and the second of the three communications lines;

means for applying a second binary state to the first and the second of the three communications lines after the false address is coupled to the first and the second of the three communications lines; and

means for applying the binary bits of the second data message to the second of the three communications lines while the second binary state is applied to the first of the three communications lines.

2. A master data device in accordance with claim 1 wherein the means for coupling the first data message further comprises means for applying, for each bit of the first data message, a second binary state to the first of the three communications lines and the first binary state to the second of the three communications lines during at least part of the time a first data message bit has a binary zero state, and applying the first binary state to the first of the three communications lines and the second binary state to the second of the three communications lines during at least part of the time a first data message bit has a binary one state.

3. A master data device in accordance with claim 2 wherein the means for applying, for each bit of the first data message, a second binary state further comprises means for applying the second binary state to the first and the second of the three communications lines between successive bits of the first data message.

4. A master data device in accordance with claim 1 further comprising means for receiving from the slave data device on the third of the three communications lines a third data message at the second rate of data transfer while the second binary state is applied to the first of the three communications lines.

5. A master data device in accordance with claim 1 further comprising means for successively applying the first binary state to the first and second of the three communications lines following applying the binary bits of the second data message to the second of the three communications lines.

6. A master data device in accordance with claim 4 further comprising means for successively applying the first binary state to the first and second of the three communications lines following receipt of the third data message.

7. A slave data device employing a data transmission bus including three communications lines for receiving a first data message transmitted from a master data device at a first rate of data transfer, for receiving a second data message transmitted from the master data device at a second rate of data transfer, and for communicating a third data message to the master data device, each of the three data messages having a plurality of binary bits, each bit having either a binary zero state or a binary one state for a period of time which is related to the data transfer rate, the slave data device comprising:

means for receiving a first binary state from a first and a second of the three communications lines before and after the first data message;

means for receiving the first data message from the first and second of the three communications lines;

means for coupling at the first rate of data transfer the binary bits of the third data message to a third of the three communications lines;

means for receiving a false address of the first data message from the first and the second of the three communications lines;

means for receiving a second binary state from the first and the second of the three communications lines after the false address is received from the first and the second of the three communications lines; and

means for receiving the binary bits of the second data message from the second of the three communications lines while the second binary state is received from the first of the three communications lines.

8. A slave data device in accordance with claim 7 wherein the means for receiving the first data message further comprises means for receiving, for each bit of the first data message, a second binary state from the first of the three communications lines and the first binary state from the second of the three communications lines during at least part of the time a first data message bit has a binary zero state, and receiving the first binary state from the first of the three communications lines and the second binary state from the second of the three communications lines during at least part of the time a first data message bit has a binary one state.

9. A slave data device in accordance with claim 8 wherein the means for receiving, for each bit of the first data message, a second binary state further comprises means for receiving the second binary state from the first and the second of the three communications lines between successive bits of the first data message.

10. A slave data device in accordance with claim 7 further comprising means for communicating to the master data device on the third of the three communications lines a third data message at the second rate of data transfer while the second binary state is applied to the first of the three communications lines.

11. A slave data device in accordance with claim 7 further comprising means for successively receiving the first binary state from the first and second of the three communications lines following receiving the binary bits of the second data message from the second of the three communications lines.

12. A slave data device in accordance with claim 10 further comprising means for successively receiving the first binary state from the first and second of the three communications lines following receipt of the third data message.

13. A data transmission system including three communications lines for communicating a first data message from a first data device to a second data device at a first rate of data transfer, for communicating a second data message from the first data device to the second data device at a second rate of data transfer, and for communicating a third data message from the second data device to the first data device, each of the three data messages having a plurality of binary bits, each bit having either a binary zero state or a binary one state for a period of time which is related to the data transfer rate, the data transmission system comprising:

means, at the first data device, for applying a first binary state to a first and a second of the three communications lines before and after the first data message;

means, at the first data device, for coupling the first data message to the first and second of the three communications lines;

means, at the second data device, for coupling at the first rate of data transfer the binary bits of the third data message to a third of the three communications lines;

means, at the first data device, for coupling a false address of the first data message to the first and the second of the three communications lines;

means, at the first data device, for applying a second binary state to the first and the second of the three communications lines after the false address is coupled to the first and the second of the three communications lines; and

means, at the first data device, for applying the binary bits of the second data message to the second of the three communications lines while the second binary state is applied to the first of the three communications lines.

14. A data transmission system in accordance with claim 13 wherein the means, at the first data device, for coupling the first data message further comprises means, at the first data device, for applying, for each bit of the first data message, a second binary state to the first of the three communications lines and the first binary state to the second of the three communications lines during at least part of the time a first data message bit has a binary zero state, and applying the first binary state to the first of the three communications lines and the second binary state to the second of the three communications lines during at least part of the time a first data message bit has a binary one state.

15. A data transmission system in accordance with claim 14 wherein the means for applying, for each bit of the first data message, a second binary state further comprises means, at the first data device, for applying the second binary state to the first and the second of the three communications lines between successive bits of the first data message.

16. A data transmission system in accordance with claim 13 further comprising means, at the first data device, for receiving from the second data device on the third of the three communications lines a third data message at the second rate of data transfer while the second binary state is applied to the first of the three communications lines.

17. A data transmission system in accordance with claim 13 further comprising means, at the first data device, for successively applying the first binary state to the first and second of the three communications lines following applying, at the first data device, the binary bits of the second data message to the second of the three communications lines.

18. A master data device in accordance with claim 16 further comprising means, at the first data device, for successively applying the first binary state to the first and second of the three communications lines following receipt, at the first data device, of the third data message.

19. A portable radiotelephone apparatus employing a data transmission bus including three communications lines for communicating a first data message to a peripheral data device at a first rate of data transfer, for communicating a second data message to the peripheral data device at a second rate of data transfer, and for receiving a third data message from the peripheral data device, each of the three data messages having a plurality of binary bits, each bit having either a binary zero state or a binary one state for a period of time which is related to the data transfer rate, the portable radiotelephone apparatus comprising:

means for applying a first binary state to a first and a second of the three communications lines before and after the first data message;

means for coupling the first data message to the first and second of the three communications lines;

means for receiving from the peripheral data device the binary bits of the third data message at the first rate of data transfer from a third of the three communications lines;

means for coupling a false address of the first data message to the first and the second of the three communications lines;

means for applying a second binary state to the first and the second of the three communications lines after the false address is coupled to the first and the second of the three communications lines;

means for applying the binary bits of the second data message to the second of the three communications lines while the second binary state is applied to the first of the three communications lines; and

means for receiving from the peripheral data device the binary bits of the third data message at the second rate of data transfer on the third of the three communications lines while the second binary state is applied to the first of the three communications lines.

20. A peripheral data device employing a data transmission bus including three communications lines for receiving a first data message from a portable radiotelephone apparatus at a first rate of data transfer, for receiving a second data message from the portable radiotelephone apparatus at a second rate of data transfer, and for communicating a third data message to the portable radiotelephone apparatus, each of the three data messages having a plurality of binary bits, each bit having either a binary zero state or a binary one state for a period of time which is related to the data transfer rate, the peripheral data device comprising:

means for receiving a first binary state from a first and a second of the three communications lines before and after the first data message;

means for receiving the first data message from the first and second of the three communications lines;

means for applying the binary bits of the third data message at the first rate of data transfer to a third of the three communications lines;

means for receiving a false address of the first data message from the first and the second of the three communications lines;

means for receiving a second binary state from the first and the second of the three communications lines after the false address is received from the first and the second of the three communications lines;

means for receiving the binary bits of the second data message from the second of the three communications lines while the second binary state is applied to the first of the three communications lines; and

means for coupling to the third of the three communications lines a third data message at the second rate of data transfer while the second binary state is applied to the first of the three communications lines.

21. A master data device employing a data transmission bus including three communications lines for transmitting a first data message from the master data device to a slave data device at a first rate of data transfer and for transmitting a second data message from the master data device to the slave data device at a second rate of data transfer, each of the two data messages having a plurality of binary bits, each bit having either a binary zero state or a binary one state for a period of time which is related to the data transfer rate, the master data device comprising:

a data bus controller for;

applying a first binary state to a first and a second of the three communications lines before and after the first data message;

coupling the first data message to the first and second of the three communications lines;

coupling a false address of the first data message to the first and the second of the three communications lines;

applying a second binary state to the first and the second of the three communications lines after the false address is coupled to the first and the second of the three communications lines; and

applying the binary bits of the second data message to the second of the three communications lines while the second binary state is applied to the first of the three communications lines.

22. A slave data device employing a data transmission bus including three communications lines for receiving a first data message transmitted from a master data device at a first rate of data transfer, for receiving a second data message transmitted from the master data device at a second rate of data transfer, and for communicating a third data message to the master data device, each of the three data messages having a plurality of binary bits, each bit having either a binary zero state or a binary one state for a period of time which is related to the data transfer rate, the slave data device comprising:

a data bus controller for;

receiving a first binary state from a first and a second of the three communications lines before and after the first data message;

receiving the first data message from the first and second of the three communications lines;

coupling at the first rate of data transfer the binary bits of the third data message to a third of the three communications lines;

receiving a false address of the first data message from the first and the second of the three communications lines;

receiving a second binary state from the first and the second of the three communications lines after the false address is received from the first and the second of the three communications lines; and

receiving the binary bits of the second data message from the second of the three communications lines while the second binary state is received from the first of the three communications lines.

23. A master data device employing a data transmission bus that is configured either as a synchronous data transmission bus for transmitting messages from the master data device to a slave data device at a first rate of data transfer or as a asynchronous data transmission bus for transmitting messages from the master data device to the slave data device at a second rate of data transfer, the master data device comprising:

means for communicating the messages on the synchronous data transmission bus to the slave data device;

means for configuring the data transmission bus so that the slave data device ignores further messages on the synchronous data transmission bus;

means for configuring the data transmission bus so that the slave data device does not communicate messages on the synchronous data transmission bus; and

means for configuring the data transmission bus as a full-duplex asynchronous data transmission bus for communicating messages between the master data device and the slave data device, wherein the master data device communicates messages to the slave data device on a first communication line of three communication lines of the data transmission bus and wherein the the slave data device communicates messages to the master data device on a second communication line of the three communication lines of the data transmission bus.

24. A slave data device employing a data transmission bus that is configured either as a synchronous data transmission bus for receiving messages transmitted from the master data device to the slave data device at a first rate of data transfer or as a asynchronous data transmission bus for receiving messages transmitted from the master data device to the slave data device at a second rate of data transfer, the slave data device comprising:

means for receiving the first data message on the synchronous data transmission bus transmitted from the master data device;

means for receiving an indication from the master data device to ignore further messages on the synchronous data transmission bus;

means for receiving an indication from the master data device not to communicate messages on the synchronous data transmission bus; and

means for configuring the data transmission bus as a full-duplex asynchronous data transmission bus for communicating messages between the master data device and the slave data device, wherein the master data device communicates messages to the slave data device on a first communication line of three communication lines of the data transmission bus and wherein the the slave data device communicates messages to the master data device on a second communication line of the three communication lines of the data transmission bus.

25. A method of data transmission on a data transmission bus including three communications lines for transmitting a first data message from a first data device to a second data device at a first rate of data transfer and for transmitting a second data message from the first data device to the second data device at a second rate of data transfer, each of the two data messages having a plurality of binary bits, each bit having either a binary zero state or a binary one state for a period of time which is related to the data transfer rate, the method of data transmission comprising the steps of:

applying a first binary state to a first and a second of the three communications lines before and after the first data message;

coupling the first data message to the first and second of the three communications lines;

coupling a false address of the first data message to the first and the second of the three communications lines;

applying a second binary state to the first and the second of the three communications lines after the step of coupling false address the first and the second of the three communications lines; and

applying the binary bits of the second data message to the second of the three communications lines while the second binary state is applied to the first of the three communications lines.

26. A method of data transmission in accordance with claim 25 wherein the means for coupling the first data message further comprises the steps of applying, for each bit of the first data message, a second binary state to the first of the three communications lines and the first binary state to the second of the three communications lines during at least part of the time a first data message bit has a binary zero state;

and applying the first binary state to the first of the three communications lines and the second binary state to the second of the three communications lines during at least part of the time a first data message bit has a binary one state.

27. A method of data transmission in accordance with claim 26 wherein the step of applying, for each bit of the first data message, a second binary state further comprises the step of applying the second binary state to the first and the second of the three communications lines between successive bits of the first data message.

28. A method of data transmission in accordance with claim 25 further comprising the step of receiving from the second data device on the third of the three communications lines a third data message at the second rate of data transfer while the second binary state is applied to the first of the three communications lines.

29. A method of data transmission in accordance with claim 25 further comprising the step of successively applying the first binary state to the first and second of the three communications lines following applying the binary bits of the second data message to the second of the three communications lines.

30. A method of data transmission in accordance with claim 27 further comprising the step of successively applying the first binary state to the first and second of the three communications lines following receipt of the third data message.

31. A method, performed by a master data device, for configuring a data transmission bus as a synchronous data transmission bus for transmitting messages from the master data device to a slave data device at a first rate of data transfer or as a asynchronous data transmission bus for transmitting messages from the master data device to the slave data device at a second rate of data transfer, the method, performed by the master data device, for configuring the data transmission bus comprising the steps of:

communicating the messages on the synchronous data transmission bus to the slave data device;

configuring the data transmission bus so that the slave data device ignores further messages on the synchronous data transmission bus;

configuring the data transmission bus so that the slave data device does not communicate messages on the synchronous data transmission bus; and

configuring the data transmission bus as a full-duplex asynchronous data transmission bus for communicating messages between the master data device and the slave data device, wherein the master data device communicates messages to the slave data device on a first communication line of three communication lines of the data transmission bus and wherein the the slave data device communicates messages to the master data device on a second communication line of the three communication lines of the data transmission bus.

32. A method, performed by a slave data device, for configuring a data transmission bus as a synchronous data transmission bus for receiving messages transmitted from a master data device to the slave data device at a first rate of data transfer or as a asynchronous data transmission bus for receiving messages transmitted from the master data device to the slave data device at a second rate of data transfer, the method, performed by the slave data device, for configuring the data transmission bus comprising the steps of:

receiving the first data message on the synchronous data transmission bus transmitted from the master data device;

receiving an indication from the master data device to ignore fuller messages on the synchronous data transmission bus;

receiving an indication from the master data device not to communicate messages on the synchronous data transmission bus; and

configuring the data transmission bus as a full-duplex asynchronous data transmission bus for communicating messages between the master data device and the slave data device, wherein the master data device communicates messages to the slave data device on a first communication line of three communication lines of the data transmission bus and wherein the the slave data device communicates messages to the master data device on a second communication line of the three communication lines of the data transmission bus.