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Processor with an addressable address translation buffer operative in associative and non-associative modes

  • US 5,835,963 A
  • Filed: 09/07/1995
  • Issued: 11/10/1998
  • Est. Priority Date: 09/09/1994
  • Status: Expired due to Fees
First Claim
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1. A data processor comprising:

  • a central processing unit generating addresses in an address space; and

    an address translation unit including an address translation buffer and a controller,wherein the address translation buffer includes a plurality of entries for address translation and is addressable in the address space of the central processing unit,wherein the controller is supplied with data and an address having an association bit from the central processing unit and the controller controls associative writing, andwherein the controller enables data to be written to a predetermined bit in an entry designated by an address from the central processing unit if a searched address information in an entry of the address translation buffer corresponds to information in the address from the central processing unit, and the controller inhibits data to be written to the predetermined bit in the entry designated by the address from the central processing unit if the searched address information in the entry of the address translation buffer does not correspond to the information in the address from the central processing unit, when an association bit of an address is in a first state.

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