Processor with an addressable address translation buffer operative in associative and non-associative modes

• US 5,835,963 A
• Filed: 09/07/1995
• Issued: 11/10/1998
• Est. Priority Date: 09/09/1994
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yoshioka, Shinichi, Narita, Susumu, Tamaki, Saneaki, Kawasaki, Ikuya
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): CHOW, CHRISTOPHER S
• Application Number:
  US08/524,791
• Time in Patent Office: 1,160 Days
• Field of Search: 395/416, 395/417, 395/450, 365/49, 711/206, 711/207, 711/123
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1054 the data cache being concurrently physically addressed
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory
• CPC Class Codes: G06F 2212/652 Page size control
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells

Abstract

A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

Claims

1. A data processor comprising:

a central processing unit generating addresses in an address space; and

an address translation unit including an address translation buffer and a controller,

wherein the address translation buffer includes a plurality of entries for address translation and is addressable in the address space of the central processing unit,

wherein the controller is supplied with data and an address having an association bit from the central processing unit and the controller controls associative writing, and

wherein the controller enables data to be written to a predetermined bit in an entry designated by an address from the central processing unit if a searched address information in an entry of the address translation buffer corresponds to information in the address from the central processing unit, and the controller inhibits data to be written to the predetermined bit in the entry designated by the address from the central processing unit if the searched address information in the entry of the address translation buffer does not correspond to the information in the address from the central processing unit, when an association bit of an address is in a first state.

2. The data processor according to claim 1, wherein the controller enables data to be written to the predetermined bit in the entry designated by the address from the central processing unit independent of whether the searched address information in the entry of the address translation buffer corresponds to information in the address from the central processing unit, when the association bit of the address is in a second state.

3. The data processor according to claim 2,

wherein the predetermined bit comprises a bit for indicating whether the entry is valid.

4. The data processor according to claim 3,

wherein the address translation unit includes a comparator that compares searched address information in the entry of the address translation buffer with information in the address from the central processing unit and outputs a hit signal when the searched address information in the entry of the address translation buffer corresponds to the information in the address from the central processing unit,

wherein the controller includes a write control circuit supplying data to be written to the address translation buffer and a logic circuit supplied with the association bit and the hit signal and outputting either a first control signal or a second control signal to the write control circuit,

wherein the logic circuit outputs the first control signal to the write control circuit when the association bit of the second state is supplied to the logic circuit, and the logic circuit outputs the first control signal to the write control circuit when the association bit of the first state and the hit signal are supplied to the logic circuit, and

wherein the write control circuit supplies data to be written to the valid bit in the entry designated by the address from the central processing unit when the write control circuit is supplied with the first control signal, wherein the valid bit is rewritten by the data.

5. The data processor according to claim 4,

wherein the logic circuit outputs the second control signal to the write control circuit when the association bit of the first state is supplied to the logic circuit if the hit signal is not supplied to the logic circuit, and

wherein the write control circuit does not supply data to be written to the valid bit in the entry designated by the address from the central processing unit when the write control circuit is supplied with the second control signal, wherein the valid bit is not rewritten by the data.

6. The data processor according to claim 5,

wherein the first state of the association bit comprises a logic "1", and the second state of the association bit comprises a logic "0".

7. The data processor according to claim 6,

wherein first and second registers are designated by a MOVE instruction executed by the central processing unit, wherein the first register stores an address of one of the plurality of entries and the association bit, wherein the second register stores data to be written in the one of the plurality of entries.

8. The data processor according to claim 7,

wherein the address translation unit comprises a set associative address translation unit.

9. A data processor comprising:

a central processing unit generating addresses in an address space and operable in a privileged mode and a user mode, wherein the central processing unit can execute a set of instructions in the privileged mode, wherein the central processing unit can execute only a subset of the set of instructions in the user mode; and

an address translation unit including an address translation buffer and a controller,

wherein the address translation buffer includes a plurality of entries for address translation and is addressable in the address space of the central processing unit,

wherein the controller is supplied with data and an address having an association bit from the central processing unit and the controller controls associative writing in response to the central processing unit executing an instruction of the subset of instructions in the user mode,

wherein the controller enables data to be written to a predetermined bit in an entry designated by an address from the central processing unit if a searched address information in an entry of the address translation buffer corresponds to information in the address from the central processing unit, and the controller inhibits data to be written to the predetermined bit in the entry designated by the address from the central processing unit if the searched address information in the entry of the address translation buffer does not correspond to the information in the address from the central processing unit, when an association bit of an address is in a first state.

10. The data processor according to claim 9, wherein the controller enables data to be written to the predetermined bit in the entry designated by the address from the central processing unit independent of whether the searched address information in the entry of the address translation buffer corresponds to information in the address from the central processing unit, when the association bit of the address is in a second state.

11. The data processor according to claim 10,

wherein the predetermined bit comprises a bit for indicating whether the entry is valid.

12. The data processor according to claim 11,

wherein the address translation unit includes a comparator that compares a searched address information in the entry of the address translation buffer with information in the address from the central processing unit and outputs a hit signal when the searched address information in the entry of the address translation buffer corresponds to the information in the address from the central processing unit,

wherein the controller includes a write control circuit supplying data to be written to the address translation buffer and a logic circuit supplied with the association bit and the hit signal and outputting either a first control signal or a second control signal to the write control circuit,

wherein the logic circuit outputs the first control signal to the write control circuit when the association bit of the second state is supplied to the logic circuit, and the logic circuit outputs the first control signal to the write control circuit when the association bit of the first state and the hit signal are supplied to the logic circuit, and

wherein the write control circuit supplies data to be written to the valid bit in the entry designated by the address from the central processing unit when the write control circuit is supplied with the first control signal, wherein the valid bit is rewritten by the data.

13. The data processor according to claim 12,

wherein the logic circuit outputs the second control signal to the write control circuit when the association bit of the first state is supplied to the logic circuit if the hit signal is not supplied to the logic circuit,

wherein the write control circuit does not supply data to be written to the valid bit in the entry designated by the address from the central processing unit when the write control circuit is supplied with the second control signal, wherein the valid bit is not rewritten by the data.

14. The data processor according to claim 13,

wherein the first state of the association bit comprises a logic "1", and the second state of the association bit comprises a logic "0".

15. The data processor according to claim 14,

wherein the instruction of the subset of instructions executed by the central processing unit in the user mode is a MOVE instruction for instructing data transfer.

16. The data processor according to claim 15,

wherein first and second registers are designated by the MOVE instruction, wherein the first register stores an address of one of the plurality of entries for address translation and the association bit, wherein the second register stores data to be written in the one of the plurality of entries for address translation.

17. The data processor according to claim 16,

wherein the address translation unit comprises a set associative address translation unit.

18. A data processor comprising:

a central processing unit generating addresses in an address space and including a plurality of registers; and

an address translation unit including an address translation buffer and a controller,

wherein the address translation buffer includes a plurality of entries for address translation and is addressable in the address space of the central processing unit,

wherein the controller is supplied with data stored in a first register of the plurality of registers and is supplied with an address including an association bit stored in a second register of the plurality of registers, wherein the controller controls associative writing in response to the central processing unit executing an instruction, and

wherein the controller enables data stored in the first register to be written to a predetermined bit in an entry designated by the address stored in the second register if a searched address information in an entry of the address translation buffer corresponds to information in the address stored in the second register, and the controller inhibits data stored in the first register to be written to the predetermined bit in the entry of the address translation buffer if the searched address information in the entry of the address translation buffer does not correspond to the information in the address stored in the second register, when an association bit of an address is in a first state.

19. The data processor according to claim 18, wherein the controller enables data stored in the first register to be written to the predetermined bit in the entry designated by the address stored in the second register independent of whether the searched address information in the entry of the address translation buffer corresponds to information in the address stored in the second register, when the association bit of the address is in a second state.

20. The data processor according to claim 19,

wherein the predetermined bit comprises a bit for indicating whether the entry is valid.

21. The data processor according to claim 20,

wherein the address translation unit includes a comparator that compares a searched address information in the entry of the address translation buffer with information in the address stored in the second register and outputs a hit signal when the searched address information in the entry of the address translation buffer corresponds to the information in the address stored in the second register,

wherein the controller includes a write control circuit supplying data to be written to the address translation buffer and a logic circuit supplied with the association bit and the hit signal and outputting either a first control signal or a second control signal to the write control circuit,

wherein the logic circuit outputs the first control signal to the write control circuit when the association bit of the second state is supplied to the logic circuit, and the logic circuit outputs the first control signal to the write control circuit when the association bit of the first state and the hit signal are supplied to the logic circuit, and

wherein the write control circuit supplies data to be written to the valid bit in the entry designated by the address stored in the second register when the write control circuit is supplied with the first control signal, wherein the valid bit is rewritten by the data.

22. The data processor according to claim 21,

wherein the logic circuit outputs the second control signal to the write control circuit when the association bit of the first state is supplied to the logic circuit if the hit signal is not supplied to the logic circuit,

wherein the write control circuit does not supply data to be written to the valid bit in the entry designated by the address stored in the second register when the write control circuit is supplied with the second control signal, wherein the valid bit is not rewritten by the data.

23. The data processor according to claim 22,

wherein the first state of the association bit comprises a logic "1", and the second state of the association bit comprises a logic "0".

24. The data processor according to claim 23,

wherein the instruction executed by the central processing unit comprises a MOVE instruction for instructing data transfer.

25. The data processor according to claim 24,

wherein the address translation unit comprises a set associative address translation unit.

28. The data processor according to claim 22,

wherein the predetermined bit comprises a valid bit for indicating whether the entry is valid.

29. The data processor according to claim 28,

wherein the address translation unit includes a comparator that compares a searched address information in the entry of the address translation buffer with information in the address stored in the second register and outputs a hit signal when the searched address information in the entry of the address translation buffer corresponds to the information in the address stored in the second register,

wherein the controller includes a write control circuit supplying data to be written to the address translation buffer and a logic circuit supplied with the association bit and the hit signal and outputting either a first control signal or a second control signal to the write control circuit,

wherein the logic circuit outputs the first control signal to the write control circuit when the association bit of the second state is supplied to the logic circuit, and the logic circuit outputs the first control signal to the write control circuit when the association bit of the first state and the hit signal are supplied to the logic circuit, and

wherein the write control circuit supplies data to be written to the valid bit in the entry designated by the address stored in the second register when the write control circuit is supplied with the first control signal, wherein the valid bit is rewritten by the data.

30. The data processor according to claim 29,

wherein the logic circuit outputs the second control signal to the write control circuit when the association bit of the first state is supplied to the logic circuit if the hit signal is not supplied to the logic circuit,

wherein the write control circuit does not supply data to be written to the valid bit in the entry designated by the address stored in second register when the write control circuit is supplied with the second control signal, wherein the valid bit is not rewritten by the data.

31. The data processor according to claim 30, wherein the first state of the association bit comprises a logic "1", and the second state of the association bit comprises a logic "0".

32. The data processor according to claim 31,

wherein the address translation unit comprises a set associative address translation unit.

26. A data processor comprising:

a central processing unit generating addresses in an address space and including a plurality of registers; and

an address translation unit including an address translation buffer and a controller,

wherein the address translation buffer includes a plurality of entries for address translation and is addressable in the address space of the central processing unit,

wherein the controller is supplied with data stored in a first register of the plurality of registers and is supplied with an address including an association bit stored in a second register of the plurality of registers, wherein the controller controls associative writing in response to the central processing unit executing a MOVE instruction for instructing data transfer, and

wherein the controller enables the data stored in the first register to be written to a predetermined bit in an entry designated by the address stored in the second register if a searched address information in an entry of the address translation buffer corresponds to information in the address stored in the second register, and the controller inhibits the data stored in the first register to be written to the predetermined bit in the entry if the searched address information in the entry of the address translation buffer does not correspond to the information in the address stored in the second register, when an association bit of an address is in a first state.

27. The data processor according to claim 26, wherein the controller enables data stored in the first register to be written to the predetermined bit in the entry designated by the address stored in the second register independent of whether the searched address information in the entry of the address translation buffer corresponds to information in the address stored in the second register, when the association bit of the address is in a second state.