Process for bonding a shell to a substrate for packaging a semiconductor

• US 5,837,562 A
• Filed: 07/07/1995
• Issued: 11/17/1998
• Est. Priority Date: 07/07/1995
• Status: Expired due to Term

• Current Assignee: Charles Stark Draper Laboratory Incorporated
• Original Assignee: Charles Stark Draper Laboratory Incorporated
• Inventors: Cho, Steve T.
• Primary Examiner(s): GRAYBILL, DAVID E
• Application Number:
  US08/499,411
• Time in Patent Office: 1,229 Days
• Field of Search: 257/704, 257/682, 257/698, 437/210, 437/215, 437/218, 437/7, 438/51, 438/88, 438/118, 438/125, 438/456, 438/466, 438/611, 438/654, 438/656, 438/661, 438/685, 438/686, 438/761
• US Class Current: 438/51
• CPC Class Codes: G01P 1/023 for acceleration measuring devices
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/163 Connection portion, e.g. seal

Abstract

A process for manufacturing a vacuum enclosure for a semiconductor device formed on a substrate with leads extending peripherally. Assembly of the enclosure is compatible with known batch fabrication techniques and is carried out at pressures required for optimal device operation. In a first embodiment, an intrinsic silicon shell is sealed to the substrate via electrostatic or anodic bonding with the leads diffusing into the shell. In a second embodiment, a thin interface layer of silicon or polysilicon is deposited on the substrate prior to electrostatic bonding a glass shell thereon. In a third embodiment, tunnels are formed between a lower peripheral edge of the shell and the substrate, allowing leads to pass thereunder. The tunnels are sealed by a dielectric material applied over the enclosure.

Claims

1. A method for forming a vacuum enclosure enclosing a semiconductor device, said method comprising:

providing a substrate;

disposing a semiconductor device on said substrate;

forming a plurality of electrical leads in communication with said semiconductor device on said substrate, wherein said step of forming further comprises

depositing a lower layer of refractory metal on said substrate, and

depositing an upper layer of soft metal over said lower layer;

positioning a shell having a concave surface with surrounding edges on said substrate, on said plurality of electrical leads, and over said semiconductor device; and

anodically bonding said shell to said substrate, including eutectically sealing said shell edges to said upper layer of each of said plurality of electrical leads.

2. The method according to claim 1, wherein said step of providing a substrate includes providing a glass substrate.

3. The method according to claim 1, wherein said step of disposing said semiconductor device includes fabricating said semiconductor device on said substrate.

4. The method according to claim 1, wherein said step of positioning said shell further comprises positioning a high-resistivity silicon shell.

5. The method according to claim 1, wherein said step of positioning said shell further comprises depositing a high-resistivity silicon layer on said shell lower edge.

6. The method according to claim 5, wherein said step of bonding further comprises eutectically sealing said silicon layer to said plurality of electrical leads.

7. The method according to claim 1, wherein said step of positioning said shell further comprises aligning a plurality of ports disposed in said shell edges with respective ones of said plurality of electrically conductive leads.

8. The method according to claim 7, wherein said step of bonding said shell further includes depositing a dielectric sealing material about said shell edges and within said plurality of ports.

9. The method according to claim 8, further including the step of etching said dielectric sealing material to expose electrically conductive pads proximate said shell.

10. The method according to claim 1, before the step of anodically bonding, further including:

inserting spacers between said shell and said substrate;

backfilling said enclosure with inert gas to evacuate moisture from within said enclosure;

subjecting said enclosure to anodic bonding conditions to electrostatically outgas materials from said enclosure which could adversely effect subsequent bonding; and

removing said spacers.

11. A method for forming a vacuum enclosure enclosing a semiconductor device, said method comprising:

providing a substrate;

disposing a semiconductor device on said substrate;

forming a plurality of electrical leads in communication with said semiconductor device on said substrate;

positioning a shell having a concave surface with surrounding edges on said substrate, on said plurality of electrical leads, and over said semiconductor device;

inserting spacers between said shell and said substrate;

backfilling said enclosure with inert gas to evacuate moisture from within said enclosure;

subjecting said enclosure to anodic bonding conditions to electrostatically outgas materials from said enclosure which could adversely effect subsequent bonding;

removing said spacers; and

bonding said shell to said substrate.