Vertical interconnect process for silicon segments

• US 5,837,566 A
• Filed: 04/24/1997
• Issued: 11/17/1998
• Est. Priority Date: 06/23/1994
• Status: Expired due to Term

• Current Assignee: Vertical Circuits Solutions, Inc.
• Original Assignee: Cubic Memory, Inc.
• Inventors: Finley, Michael G., Pedersen, David V., Sautter, Kenneth M.
• Primary Examiner(s): Graybill, David
• Assistant Examiner(s): Zarneke, David A.
• Application Number:
  US08/847,309
• Time in Patent Office: 572 Days
• Field of Search: 438/107, 438/109, 438/110, 438/112, 438/113, 438/118, 438/119
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29399 Coating material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/3737 : Organic materials with or without a thermoconductive filler
• CPC Class Codes: H01L 23/4824 : Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/5256 : comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/5328 : containing conductive organic materials or pastes, e.g. conductive adhesives, inks
• CPC Class Codes: H01L 23/5382 : Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H01R 29/00 : Coupling parts for selective co-operation with a counterpart in different ways to establish different circuits, e.g. for voltage selection, for series-parallel selection, programmable connectors
• CPC Class Codes: H01R 4/04 : using electrically conductive adhesives
• CPC Class Codes: H05K 2201/09472 : Recessed pad for surface mounting recess in pad H05K2201/09745; Recessed electrode of component
• CPC Class Codes: H05K 2201/10477 : Inverted
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10719 : Land grid array [LGA]
• CPC Class Codes: H05K 2201/10727 : Leadless chip carrier [LCC], e.g. chip-modules for cards
• CPC Class Codes: H05K 3/305 : Affixing by adhesive
• CPC Class Codes: H05K 3/321 : by conductive adhesives
• CPC Class Codes: H05K 7/023 : Stackable modules
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. The stack of electrically interconnected segments is then mounted below the surface of a circuit board and electrically connected to circuits on the board by applying traces of electrically conductive epoxy between the bonding pads on the top segment of the stack and the circuit board.

Claims

1. A method for forming a stack of segments, comprising the steps of:

providing a wafer having a plurality of die;

creating a plurality of segments, each one of said plurality of segments formed by grouping a plurality of adjacent ones of said die on said wafer,

interconnecting said plurality of adjacent die on said each one of said plurality of segments;

separating said each one of said plurality of segments from said wafer;

placing said plurality of segments on top of one another to create a stack of segments, said stack having external vertical sides;

electrically interconnecting said stack of segments;

providing internal electrically conductive contact points on each of said plurality of die;

providing external electrically conductive contact points said each one of said plurality of segments;

providing a layer of metal traces on said each one of said plurality of segments, said metal traces extending between said internal electrically conductive contact points on said plurality of die and said external electrically conductive contact points on said each one of said plurality of segments; and

applying electrically conductive epoxy to more than one of said external vertical sides of said stack such that said electrically conductive epoxy is in contact with said external electrically conductive contact points on said each one of said segments in said stack, to thereby electrically interconnect said plurality of segments in said stack.

2. A method for forming a stack of segments as in claim 1 further including the steps of:

providing control bond pads on each of said segments;

providing control signals to said stack from an external source for access to said segments in said stack; and

making said control signals for each of said segments unique by burning a unique pattern into said control bond pads on each of said segments.

3. A method for forming a stack of segments as in claim 2 wherein said stack includes a top segment, said method further comprising the steps of:

providing a signal carrying substrate having circuitry and a hole therein;

affixing said stack of segments in said hole; and

electrically connecting said stack of segments to said signal carrying substrate by applying traces of electrically conductive epoxy between said signal carrying substrate and said external electrically conductive contact points on said top segment of said stack.

4. A method for forming a stack of segments as in claim 3 wherein said top stack is co-planer with the surface of said signal carrying substrate.

5. A method for forming a stack of segments as in claim 4 wherein said traces of electrically conductive epoxy lie in substantially the same plane as said signal caring substrate.