Enhanced planarization technique for an integrated circuit

• US 5,837,613 A
• Filed: 11/24/1997
• Issued: 11/17/1998
• Est. Priority Date: 12/06/1993
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Kalnitsky, Alex, Lin, Yih-Shung
• Primary Examiner(s): POWELL, WILLIAM A
• Application Number:
  US08/976,760
• Time in Patent Office: 358 Days
• Field of Search: 216/18, 216/19, 216/38, 216/39, 216/80, 216/88, 216/97, 216/99, 438/691, 438/692, 438/697, 438/699, 438/723, 438/747, 438/631, 438/633, 438/743
• US Class Current: 438/697
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051

Abstract

A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.

Claims

1. An integrated circuit fabrication method, comprising the acts of:

(a.) providing a partially fabricated integrated circuit structure which has an uneven topography containing high points;

(b.) applying and curing spin-on glass, to form a first dielectric;

(c.) depositing dielectric material from a vapor phase, to form a second dielectric layer over said first layer;

(d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers;

(e.) substantially removing said dielectric stack from said high points of said partially fabricated structure while leaving said dielectric stack in other portions of said partially fabricated structure;

(f.) depositing an interlevel dielectric;

(g.) etching holes in said interlevel dielectric in locations; and

(h.) depositing and patterning a metallization layer to form a pattern of connections, including connections through said holes.

2. The method of claim 1, wherein said deposition act (c.) is plasma-enhanced.

3. The method of claim 1, wherein said deposition (c.) uses TEOS as a source gas.

4. The method of claim 1, comprising the additional act of applying a passivating dielectric, from a vapor phase, after said step (a.) and before said deposition step (b.).

5. The method of claim 1, wherein said deposition act (b.) applies said spin-on glass with a thickness in the range of 1000-5000 Å

.

6. The method of claim 1, wherein said deposition act (d.) applies said spin-on glass with a thickness in the range of 1000-5000 Å

.

7. The method of claim 1, wherein said interlevel dielectric is a doped silicate glass.

8. An integrated circuit fabrication method, comprising the steps of:

(a.) providing a partially fabricated integrated circuit structure which has an uneven topography containing high points;

(b.) applying and curing spin-on glass, to form a first dielectric;

(c.) depositing silicon dioxide from a vapor phase, to form a second dielectric layer over said first layer;

(d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers;

(e.) substantially removing said dielectric stack from said high points of said partially fabricated structure while leaving said dielectric stack in other portions of said partially fabricated structure;

(f.) depositing an interlevel dielectric;

(g.) etching holes in said interlevel dielectric in locations; and

(h.) depositing and patterning a metallization layer to form a pattern of connections, including connections through said holes.

9. The method of claim 8, wherein said deposition act (c.) is plasma-enhanced.

10. The method of claim 8, wherein said deposition act (c.) uses TEOS as a source gas.

11. The method of claim 8, comprising the additional act of applying a passivating dielectric, from a vapor phase, after said act (a.) and before said deposition act (b.).

12. The method of claim 8, wherein said deposition act (b.) applies said spin-on glass with a thickness in the range of 1000-5000 Å

.

13. The method of claim 8, wherein said deposition act (d.) applies said spin-on glass with a thickness in the range of 1000-5000 Å

.

14. The method of claim 8, wherein said interlevel dielectric is a doped silicate glass.

15. An integrated circuit fabrication method, comprising the acts of:

(a.) providing a partially fabricated integrated circuit structure which has an uneven topography containing high points;

(b.) applying and curing spin-on glass, to form a first dielectric layer;

(c.) depositing dielectric material from a vapor phase, to form a second dielectric layer over said first layer, said second dielectric layer having a thickness equal to or less than said first layer;

(d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers, said third dielectric layer having a thickness equal to or greater than said second layer;

(e.) substantially removing said dielectric stack from said high points of said partially fabricated structure while leaving said dielectric stack in other portions of said partially fabricated structure;

(f.) depositing an interlevel dielectric;

(g.) etching holes in said interlevel dielectric in locations; and

(h.) depositing and patterning a metallization layer to form a pattern of connections, including connections through said holes.

16. The method of claim 15, wherein said deposition act (c.) is plasma enhanced.

17. The method of claim 15, wherein said deposition act (c.) uses TEOS as a source gas.

18. The method of claim 15, comprising the additional act of applying a passivating dielectric, from a vapor phase, after said act (a.) and before said deposition act (b.).

19. The method of claim 15, wherein said deposition act (b.) applies said spin-on glass with a thickness in the range of 1000-5000 Å

.

20. The method of claim 15, wherein said interlevel dielectric is a doped silicate glass.

21. The method of claim 15, wherein said deposition act (d.) applies said spin-on glass with a thickness in the range of 1000-5000 Å

.