Ultrasonic testing (UT) system having improved signal processing

• US 5,837,899 A
• Filed: 09/13/1996
• Issued: 11/17/1998
• Est. Priority Date: 09/13/1996
• Status: Expired due to Term

• Current Assignee: Westinghouse Electric Company LLC (Brookfield Asset Management Incorporated)
• Original Assignee: Combustion Engineering Incorporated (ABB Limited)
• Inventors: Klein, Stanley, Martin, Michel St., Leonard, David S., Camerlin, Marc A., Dickerman, Robert L.
• Primary Examiner(s): Williams, Hezron E.
• Assistant Examiner(s): MILLER, ROSE MARY
• Application Number:
  US08/714,926
• Time in Patent Office: 795 Days
• Field of Search: 364/507, 364/508, 364/550, 73/609-612, 73/613-616, 73/625, 73/626, 73/628, 73/602
• US Class Current: 73/610
• CPC Class Codes: G01N 2291/011 Velocity or travel time
• CPC Class Codes: G01N 29/40 by amplitude filtering, e.g. by applying a threshold or by gain control
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979

Abstract

An ultrasonic testing system can receive data from at least two ultrasonic transducers and process the data in parallel to each other. The testing system can compress the data by a fixed ratio by storing the value of the sample having the highest-amplitude out of a group of samples. The testing system can also provide threshold-based run-length encoding by compressing data by only storing samples which exceed a user-defined threshold value as well as a user-defined range of samples surrounding said samples. The ultrasonic testing system also provides a hardware gate for storing a peak amplitude and associated time-of-flight for a user-defined interval and a gate for storing the time-of-flight for the first excursion of the data through a user-defined threshold and interval. The operation of these gates or the storage of waveform data may be delayed by a constant delay or until the data exceeds a user-selectable threshold during a user-selectable time interval. The system also provides a multi-channel design allowing simultaneous waveform and/or hardware gate acquisition of data on more than one channel and permitting the parallel processing of data.

Claims

1. An ultrasonic testing system for compressing digital data, comprising:

a pulsing circuit for stimulating an ultrasonic transducer with a voltage signal and for receiving an analog data signal from said transducer;

a timing circuit for defining acquisition intervals;

an analog-to-digital converter for converting said analog data signal into digital data at said acquisition intervals;

a counter circuit for defining user-selected groups of digital data samples;

a peak detector circuit for acquiring a peak value of said digital data within each of said groups of digital data samples; and

a memory for storing only the peak values of said digital data one from each of said groups of digital data samples, whereby said digital data is compressed to said peak values.

2. The ultrasonic testing system as set forth in claim 1, wherein said digital data is compressed by an integer ratio of 16:

1.

3. The ultrasonic testing system as set forth in claim 1, wherein said digital data is compressed by an integer ratio not less than 2:

1.

4. The ultrasonic testing system as set forth in claim 1, further comprising a second pulsing circuit for stimulating a second ultrasonic transducer with a second voltage signal and for receiving a second analog data signal from said transducer and wherein said analog-to-digital converter converts said second analog signal into second digital data and said peak detector circuit determines the peak values out of said digital data and said second digital data.

5. The ultrasonic testing system as set forth in claim 1, further comprising a control circuit for preventing said memory from storing the peak values until said digital data exceeds a threshold value during a preceding predetermined search interval.

6. An ultrasonic testing system for compressing digital data, comprising:

a pulsing circuit for stimulating an ultrasonic transducer with a voltage signal and for receiving an analog data signal from said transducer;

a timing circuit for defining acquisition intervals;

an analog-to-digital converter for converting said analog data signal into digital data at said acquisition intervals;

a counter circuit for defining user-selected groups of digital data samples;

a peak detector circuit for acquiring a peak value of said digital data within each of said groups of digital data samples; and

a memory for storing only the peak values of said digital data one from each of said groups of digital data samples, whereby said digital data is compressed to said peak values;

wherein said peak detector circuit acquires said peak value only during positive values of said analog data signal so as to result in half-wave rectification of said analog data signal.

7. An ultrasonic testing system for compressing digital data, comprising:

a pulsing circuit for stimulating an ultrasonic transducer with a voltage signal and for receiving an analog data signal from said transducer;

a timing circuit for defining acquisition intervals;

an analog-to-digital converter for converting said analog data signal into digital data at said acquisition intervals;

a counter circuit for defining user-selected groups of digital data samples;

a peak detector circuit for acquiring a peak value of said digital data within each of said groups of digital data samples; and

a memory for storing only the peak values of said digital data one from each of said groups of digital data samples, whereby said digital data is compressed to said peak values;

wherein said peak detector circuit acquires said peak value only during negative values of said analog data signal so as to result in half-wave rectification of said analog data signal.

8. An ultrasonic testing system for compressing digital data, comprising:

a pulsing circuit for stimulating an ultrasonic transducer with a voltage signal and for receiving an analog data signal from said transducer;

a timing circuit for defining acquisition intervals;

an analog-to-digital converter for converting said analog data signal into digital data at said acquisition intervals;

a counter circuit for defining user-selected groups of digital data samples;

a peak detector circuit for acquiring a peak value of said digital data within each of said groups of digital data samples; and

a memory for storing only the peak values of said digital data one from each of said groups of digital data samples, whereby said digital data is compressed to said peak values;

wherein said peak detector circuit acquires said peak value during both positive and negative values of said analog data signal so as to result in full-wave rectification of said analog data signal.

9. An ultrasonic testing system for compressing digital data, comprising:

a pulsing circuit for stimulating an ultrasonic transducer with a voltage signal and for receiving an analog data signal from said transducer;

an analog-to-digital converter for converting said analog data signal into digital data;

a threshold compare circuit for determining whether said digital data exceeds a user-selected threshold; and

a memory for storing the digital data that exceeds said user-selected threshold.

11. The ultrasonic testing system as set forth in claim 9, wherein said threshold compare circuit determines whether said digital data exceeds the user-selected threshold during a user-selected interval.

13. The ultrasonic testing system as set forth in claim 9, further comprising a control circuit for preventing said memory from storing the digital data until said digital data exceeds a second threshold value during a preceding predetermined search interval.

14. The ultrasonic testing system as set forth in claim 9, further comprising a second pulsing circuit for stimulating a second ultrasonic transducer with a second voltage signal and for receiving a second analog data signal from said transducer and wherein said analog-to-digital converter converts said second analog signal into second digital data and said threshold compare circuit determines whether said second digital data exceeds a second user-selected threshold and said memory stores said second digital data exceeding said second user-selected threshold.

10. An ultrasonic testing system for compressing digital data, comprising:

a pulsing circuit for stimulating an ultrasonic transducer with a voltage signal and for receiving an analog data signal from said transducer;

an analog-to-digital converter for converting said analog data signal into digital data;

a threshold compare circuit for determining whether said digital data exceeds a user-selected threshold; and

a memory for storing the digital data that exceeds said user-selected threshold;

wherein said memory stores digital data both before and after the data exceeding the user-selected threshold.

12. An ultrasonic testing system for compressing digital data, comprising:

a pulsing circuit for stimulating an ultrasonic transducer with a voltage signal and for receiving an analog data signal from said transducer;

an analog-to-digital converter for converting said analog data signal into digital data;

a threshold compare circuit for determining whether said digital data exceeds a user-selected threshold; and

a memory for storing the digital data that exceeds said user-selected threshold

wherein said threshold compare circuit determines whether said digital data exceeds the user-selected threshold during a user-selected interval and wherein said threshold compare circuit determines whether said digital data exceeds the user-selected threshold for a plurality of user-selected intervals.

15. An ultrasonic testing system, comprising:

a pulsing circuit for stimulating an ultrasonic transducer with a voltage signal and for receiving an analog data signal from said transducer;

an analog-to-digital converter for converting said analog data signal into digital data;

a timing circuit for defining a user-selected search interval;

a peak detector circuit for acquiring a peak value of said digital data during said user-selected search interval;

a first memory for storing said peak value of said digital data;

a timer for determining a time-of-flight associated with said peak value; and

a second memory for storing said time-of-flight.

16. The ultrasonic testing system as set forth in claim 15, wherein said timing circuit defines a plurality of user-selected search intervals, said peak detector acquiring peak values for said intervals, said first memory storing values of said peak values, said timer determining time-of-flights for said peak values, and said second memory storing said time-of-flights.

17. The ultrasonic testing system as set forth in claim 15, further comprising a control circuit for preventing said system from delaying and then searching for the peak value and the time-of-flight until said digital data exceeds a second threshold value during a preceding predetermined search interval.

18. The ultrasonic testing system as set forth in claim 15, further comprising a second pulsing circuit for stimulating a second ultrasonic transducer with a second voltage signal and for receiving a second analog data signal from said transducer and wherein said analog-to-digital converter converts said second analog signal into second digital data and said peak detector circuit acquires the peak value of said digital data and said second digital data.

19. An ultrasonic testing system, comprising:

a pulsing circuit for stimulating an ultrasonic transducer with a voltage signal and for receiving an analog data signal from said transducer;

an analog-to-digital converter for converting said analog data signal into digital data;

a timing circuit for defining a user-selected search interval;

a peak detector circuit for acquiring a peak value of said digital data during said user-selected search interval;

a first memory for storing said peak value of said digital data;

a timer for determining a time-of-flight associated with said peak value; and

a second memory for storing said time-of-flight;

wherein said peak detector circuit further determines a polarity of the peak value and said first memory stores said polarity.

20. An ultrasonic testing system, comprising:

a pulsing circuit for stimulating an ultrasonic transducer with a voltage signal and for receiving an analog data signal from said transducer;

an analog-to-digital converter for converting said analog data signal into digital data;

a timing circuit for defining a user-selected search interval;

a comparator for determining whether said digital data exceeds a user-selected threshold during said user-selected search interval;

a timer for determining a time-of-flight associated with a first data sample that exceeds said user-selected threshold; and

a memory for storing said time-of-flight.

21. The ultrasonic testing system as set forth in claim 20, further comprising a control circuit for preventing said system from delaying and then searching for a threshold crossing until said digital data exceeds a second threshold value during a preceding predetermined search interval.

22. The ultrasonic testing system as set forth in claim 20, further comprising a second pulsing circuit for stimulating a second ultrasonic transducer with a second voltage signal and for receiving a second analog data signal from said transducer and wherein said analog-to-digital converter converts said second analog signal into second digital data and comparator determines whether said second digital data exceeds a second user-selected threshold during a second user-selected interval.

23. An ultrasonic testing system, comprising:

a first pulsing circuit for stimulating a first ultrasonic transducer with a first voltage signal and for receiving a first analog data signal from said first transducer;

a second pulsing circuit for stimulating a second ultrasonic transducer with a second voltage signal and for receiving a second analog data signal from said second transducer;

analog-to-digital converting means for receiving said first and second analog data signals and for converting said first and second analog data signals into first digital data and second digital data, said analog-to-digital converting means delaying said second digital data relative to said first digital data; and

means for processing said first digital data in parallel with said second digital data.

24. The ultrasonic testing system as set forth in claim 23, wherein said analog-to-digital converting means comprises a dual channel analog-to-digital converter.

25. The ultrasonic testing system as set forth in claim 23, wherein said analog-to-digital converting means comprises a single analog-to-digital converter and said system further comprises means for demultiplexing an output of said single analog-to-digital converter into said first digital data and said second digital data.