TFT-array and manufacturing method therefor

• US 5,838,037 A
• Filed: 05/19/1997
• Issued: 11/17/1998
• Est. Priority Date: 11/15/1996
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Masutani, Yuichi, Kobayashi, Kazuhiro, Numano, Yoshinori
• Primary Examiner(s): Ngo , Ngan V.
• Application Number:
  US08/858,693
• Time in Patent Office: 547 Days
• Field of Search: 257/57, 257/61, 257/66, 257/296, 257/350
• US Class Current: 257/296
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A TFT-array including a substrate, a gate electrode, a first and second electrode provided on the substrate simultaneously with the gate electrode, an insulating film formed on the gate electrode, the first and the second electrode, a semiconductor layer formed on the gate electrode in such a manner that the insulating film is interposed between the semiconductor layer and the gate electrode, a pair of electrodes, either of which is connected with the first electrode or the second electrode, said pair of electrodes defining a semiconductor element together with the semiconductor layer.

Claims

1. A TFT-array comprising a substrate, gate electrode, a first and second electrode provided on the substrate simultaneously with the gate electrode, an insulating film formed on the gate electrode, the first and the second electrode, a semiconductor layer formed on the gate electrode in such a manner that the insulating film is interposed between the semiconductor layer and the gate electrode, a pair of electrodes, either of which is connected with the first electrode or the second electrode, said pair of electrodes defining a semiconductor element together with the semiconductor layer.

2. The TFT-array of claim 1, wherein the first electrode and the second electrode are arranged so that they are comb-shaped respectively and are opposed to each other.

3. The TFR-array of claim 1, wherein one line for forming a storage capacitance on the gate electrode side, and another line for applying the voltage upon the first electrode or the second electrode on the opposite side to the one line are formed in such a manner that the regions forming the electric field in a direction parallel to the substrate is interposed between the one line and the another line.

4. The TFT-array of claim 3, wherein the line for forming the storage capacitance and the line for applying the voltage upon the first electrode or the second electrode is electrically connected to at least one first electrode or second electrode.

5. The TFT-array of claim 1, wherein the low resisting material is connected with at least either of the line for applying the voltage upon the gate electrode, the first electrode or the second electrode or the line for forming the storage capacitance.

6. The TFT-array of claim 1, wherein whole part of the insulating film or a part of the insulating film is removed the insulating film being formed on the region for forming the electric field in the direction parallel to the substrate face.