Testing and exercising individual, unsingulated dies on a wafer

• US 5,838,163 A
• Filed: 12/26/1995
• Issued: 11/17/1998
• Est. Priority Date: 07/02/1992
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Dangelo, Carlos, Rostoker, Michael D., Koford, James
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US08/578,742
• Time in Patent Office: 1,057 Days
• Field of Search: 324/73.1, 324/158.1, 324/765, 324/763, 371/22.6, 637/8, 340/825.07, 257/40, 257/48
• US Class Current: 324/762.03
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]

Abstract

Signals (including probes) from an external system are selectively connected to a plurality of unsingulated dies on a semiconductor wafer with a minimum number of connections and an electronic selection mechanism resident on the wafer. The electronic selection mechanism is connected to the individual dies by conductive lines on the wafer. The electronic selection mechanism is capable of providing the external signals (or connecting the external probe) to a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively provide signals to the unsingulated dies.

Claims

1. A fault-tolerant method of providing signals from a common external source to individual, unsingulated dies on a semiconductor wafer, comprising:

defining a plurality of individual dies on a semiconductor wafer, said dies ultimately being processed into integrated circuit devices;

providing an electronic selection mechanism, on the wafer, for providing signals to selected individual dies; and

providing a first conductive path between said electronic selection mechanism and a first of said dies, said first conductive path comprising;

a first signal carrying line;

a second signal carrying line;

a first diode having an anode and a cathode, said first diode anode being connected to said first signal carrying line;

a second diode having an anode and a cathode, said second diode anode being connected to said second signal line; and

a first internal conductor connected to the first die, said first internal conductor being additionally connected to said first diode cathode and to said second diode cathode.

2. The method of claim 1 further comprising the step of:

applying a positive logic signal to said first conductive path.

3. The method of claim 1 further comprising the step of:

applying a positive voltage to said first conductive path.

4. The method of claim 1 further comprising the step of:

connecting said first internal conductor to a bonding pad within said first unsingulated die.

5. The method of claim 1 further comprising the step of:

providing a second conductive path between said electronic selection mechanism and the first die, said second conductive path comprising;

a third signal carrying line;

a fourth signal carrying line;

a third diode having an anode and a cathode, said third diode cathode being connected to said third signal carrying line;

a fourth diode having an anode and a cathode, said fourth diode cathode being connected to said fourth signal line;

a second internal conductor connected to the first die, said second internal conductor being additionally connected to said third diode anode and to said fourth diode anode.

6. The method of claim 5 further comprising the step of:

applying a negative logic signal to said second conductive path.

7. The method of claim 6 further comprising the step of:

applying a negative voltage to said second conductive path.