High performance self modifying on-the-fly alterable logic FPGA, architecture and method
First Claim
1. A method of configuring an array of programmable logic cells each having logic functions controlled by an associated configuration bit memory that comprises, storing bit information defining multiple program configurations in a DRAM core;
- connecting a bus to the array to enable a DRAM row wide loading of the configuration bit memories of the cells with bit information defining a desired configuration; and
, upon a configuration command, retrieving from the DRAM core, at least a row at a time, the configuration bit information, and loading such information in the bit memories of the cells to control the corresponding cell logic functions to achieve the desired configuration programming, and in which, upon completion of a function by the array of logic cells, a bit command is generated to indicate a new desired functionality of the array; and
a supplemental memory core is provided containing the bit address of a DRAM row and connected to be responsive to the next functionality bit command and correspondingly to drive the DRAM, retrieving and loading the configuration bit information representing said next functionality in the bit memories of the cells, controlling the corresponding cell logic functions and thereby self-reconfiguring the array to perform the next functionality.
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Abstract
A technique for configuring arrays of programmable logic cells, including those associated with FPGA devices, through a novel DRAM-based configuration control structure that enables not only "on-the-fly" alterable chip and similar device reconfigurations, but, where desired, self-modifying reconfigurations for differing functionalities of the devices, eliminating current serious reconfigurability limitations and related problems, while providing significantly enhanced system performance at low cost. A large amount of memory is available internal to the FPGA and is accessed with a small number of pins such that the reconfiguration time is, for example, four orders of magnitude faster than the traditional approaches and at notably low cost.
381 Citations
24 Claims
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1. A method of configuring an array of programmable logic cells each having logic functions controlled by an associated configuration bit memory that comprises, storing bit information defining multiple program configurations in a DRAM core;
- connecting a bus to the array to enable a DRAM row wide loading of the configuration bit memories of the cells with bit information defining a desired configuration; and
, upon a configuration command, retrieving from the DRAM core, at least a row at a time, the configuration bit information, and loading such information in the bit memories of the cells to control the corresponding cell logic functions to achieve the desired configuration programming, and in which, upon completion of a function by the array of logic cells, a bit command is generated to indicate a new desired functionality of the array; and
a supplemental memory core is provided containing the bit address of a DRAM row and connected to be responsive to the next functionality bit command and correspondingly to drive the DRAM, retrieving and loading the configuration bit information representing said next functionality in the bit memories of the cells, controlling the corresponding cell logic functions and thereby self-reconfiguring the array to perform the next functionality. - View Dependent Claims (2, 3)
- connecting a bus to the array to enable a DRAM row wide loading of the configuration bit memories of the cells with bit information defining a desired configuration; and
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4. A method of configuring an array of programmable logic cells each having logic functions controlled by an associated configuration bit memory, that comprises, storing bit information defining multiple program configurations in a DRAM core;
- connecting a bus to the array to enable a DRAM row wide loading of the configuration bit memories of the cells with bit information defining a desired configuration; and
, upon a configuration command, retrieving from the DRAM core, at least a row at a time, the configuration bit information, and loading such information in the bit memories of the cells to control the corresponding cell logic functions to achieve the desired configuration programming, and in which the DRAM core is also used as storage space accessible from both external I/O interfacing and internal logic. - View Dependent Claims (5, 6, 7, 8)
- connecting a bus to the array to enable a DRAM row wide loading of the configuration bit memories of the cells with bit information defining a desired configuration; and
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9. Apparatus for configuring an array of programmable logic cells each having logic functions controlled by an associated configuration bit memory, the apparatus having, in combination, a DRAM core for storing bit information defining multiple program configurations;
- a bus interconnecting the array and the DRAM core such as to enable a DRAM row wide loading of the configuration bit memories of the array of logic cells with bit information defining a desired configuration;
means for generating a configuration command; and
, upon such configuration command, and responsive thereto, means for retrieving from the DRAM core, at least a row at a time, the configuration bit information; and
means for loading such information in said bit memories of the logic cells to control the corresponding cell logic functions to achieve the desired configuration programming, and in which an access control circuit is provided connected to input the DRAM core and connected to one or both of a DRAM arbitration and refresh logic module responsive to a configuration command internally emanating from the array of logic cells, and an external DRAM interface. - View Dependent Claims (10, 11, 12, 13, 14, 15)
- a bus interconnecting the array and the DRAM core such as to enable a DRAM row wide loading of the configuration bit memories of the array of logic cells with bit information defining a desired configuration;
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16. Apparatus for configuring an array of programmable logic cells each having logic functions controlled by an associated configuration bit memory, the apparatus having, in combination, a DRAM core for storing the information defining multiple program configurations:
- a bus interconnecting the array and the DRAM core such as to enable a DRAM row wide loading of the configuration bit memories of the array of logic cells with bit information defining a desired configuration;
means for generating a configuration command; and
, upon such configuration command, and responsive thereto, means for retrieving from the DRAM core, at least a row at a time, the configuration bit information, and means for loading such information in said bit memories of the logic cells to control the corresponding cell logic functions to achieve the desired configuration programming, and in which an access control circuit is provided connected to input the DRAM core and responsive to data bits corresponding to a DRAM row address emanating from an SRAM memory core unit containing data width equal to the number of bits required to decode DRAM row addresses uniquely, thereby to drive the selected row addresses of the DRAM internally, and with the SRAM unit connected to receive address bit configuration command signals from the array of logic cells. - View Dependent Claims (17, 18)
- a bus interconnecting the array and the DRAM core such as to enable a DRAM row wide loading of the configuration bit memories of the array of logic cells with bit information defining a desired configuration;
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19. Apparatus for configuring an array of programmable logic cells each having logic functions controlled by an associated configuration bit memory, the apparatus having, in combination, a DRAM core for storing bit information defining multiple program configurations;
- a bus interconnecting the array and the DRAM core such as to enable a DRAM row wide loading of the configuration bit memories of the array of logic cells with bit information defining a desired configuration;
means for generating a configuration command; and
, upon such configuration command, and responsive thereto, means for retrieving from the DRAM core, at least a row at a time, the configuration bit information, and means for loading such information in said bit memories of the logic cells to control the corresponding cell logic functions to achieve the desired configuration programming, and in which, the logic cell array, upon completion of a function, generates a bit command to indicate a next desired functionality of the array; and
there is further provided a supplemental memory core containing the bit address of a DRAM row and connected between the array and the DRAM core to respond to said next functionality bit command and correspondingly to drive the DRAM to retrieve and load the configuration bit information representing said next functionality in the bit memories of the cells of the array, to control the corresponding cell logic functions, thereby to enable self-reconfiguration of the array to perform said next functionality. - View Dependent Claims (20, 21)
- a bus interconnecting the array and the DRAM core such as to enable a DRAM row wide loading of the configuration bit memories of the array of logic cells with bit information defining a desired configuration;
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22. Apparatus for configuring an array of programmable logic cells each having logic functions controlled by an associated configuration bit memory, the apparatus having, in combination, a DRAM core for storing bit information defining multiple program configurations;
- a bus interconnecting the array and the DRAM core such as to enable a DRAM row wide loading of the configuration bit memories of the array of logic cells with bit information defining a desired configuration;
means for generating a configuration command; and
, upon such configuration command, and responsive thereto, means for retrieving from the DRAM core, at least a row at a time, the configuration bit information; and
means for loading such information in said bit memories of the logic cells to control the corresponding cell logic functions to achieve the desired configuration programming, and in which the DRAM core is also used as storage space accessible from both external I/O interfacing and internal logic. - View Dependent Claims (23)
- a bus interconnecting the array and the DRAM core such as to enable a DRAM row wide loading of the configuration bit memories of the array of logic cells with bit information defining a desired configuration;
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24. Apparatus for configuring an array of programmable logic cells each having logic functions controlled by an associated configuration bit memory, the apparatus having, in combination, a DRAM core for storing bit information defining multiple program configurations;
- a bus interconnecting the array and the DRAM core such as to enable a DRAM row wide loading of the configuration bit memories of the array of logic cells with bit information defining a desired configuration;
means for generating a configuration command; and
, upon such configuration command, and responsive thereto, means for retrieving from the DRAM core, at least a row at a time, the configuration bit information; and
means for loading such information in said bit memories of the logic cells to control the corresponding cell logic functions to achieve the desired configuration programming, and in which the array comprises an FPGA device, and the logic cell bit memories comprises SRAM distributed bits, and in which two identical banks of DRAMs are provided with identical configuration data loaded into each, and in which when one bank is having its DRAM core(s) refreshed, the other provides the configuration data.
- a bus interconnecting the array and the DRAM core such as to enable a DRAM row wide loading of the configuration bit memories of the array of logic cells with bit information defining a desired configuration;
Specification