Correlated double sampling circuit
First Claim
1. A correlated double sampling circuit comprising:
- an input node comprising a first plate of input capacitor;
an output node;
a feedback capacitor having a first plate connected to said output node and a second plate connected to a second plate of said input capacitor;
an input transistor having a gate connected to said second plate of said input capacitor, a source connected to a first supply voltage rail, and a drain connected to said output node;
a load transistor having a gate connected to a bias node, a drain connected to said output node, and a source connected to a second supply voltage rail; and
a reset transistor connected between output node and said second plate of the input capacitor, and having a gate connected to a reset signal line.
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Abstract
A correlated double sampling circuit comprising an input node comprising a first plate of input capacitor and an output node. A first plate of a feedback capacitor is connected to the output node and a second plate of the feedback capacitor is connected to a second plate of the input capacitor. An input transistor has a gate connected to the second plate of the input capacitor, a source connected to a first supply voltage rail, and a drain connected to the output node. A load transistor has a gate connected to a bias node, a drain connected to the output node, and a source connected to a second supply voltage rail. A reset transistor is connected between output node and the second plate of the input capacitor, and has a gate connected to a reset signal line.
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Citations
1 Claim
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1. A correlated double sampling circuit comprising:
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an input node comprising a first plate of input capacitor; an output node; a feedback capacitor having a first plate connected to said output node and a second plate connected to a second plate of said input capacitor; an input transistor having a gate connected to said second plate of said input capacitor, a source connected to a first supply voltage rail, and a drain connected to said output node; a load transistor having a gate connected to a bias node, a drain connected to said output node, and a source connected to a second supply voltage rail; and a reset transistor connected between output node and said second plate of the input capacitor, and having a gate connected to a reset signal line.
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Specification
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- Resources
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Current AssigneeFoveon, Inc. (Avis Budget Group Incorporated)
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Original AssigneeFoveonics, Inc.
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InventorsMead, Carver A., Delbruck, Tobias
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Primary Examiner(s)TRAN, TOAN V
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Application NumberUS08/867,472Time in Patent Office533 DaysField of Search327/91, 327/94, 327/95, 327/33, 327/335, 327/337, 327/142, 327/198US Class Current327/95CPC Class CodesG11C 27/024 using a capacitive memory e...G11C 7/067 Single-ended amplifiers
