×

Correlated double sampling circuit

  • US 5,838,176 A
  • Filed: 06/02/1997
  • Issued: 11/17/1998
  • Est. Priority Date: 07/11/1996
  • Status: Expired due to Fees
First Claim
Patent Images

1. A correlated double sampling circuit comprising:

  • an input node comprising a first plate of input capacitor;

    an output node;

    a feedback capacitor having a first plate connected to said output node and a second plate connected to a second plate of said input capacitor;

    an input transistor having a gate connected to said second plate of said input capacitor, a source connected to a first supply voltage rail, and a drain connected to said output node;

    a load transistor having a gate connected to a bias node, a drain connected to said output node, and a source connected to a second supply voltage rail; and

    a reset transistor connected between output node and said second plate of the input capacitor, and having a gate connected to a reset signal line.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×