Method of optimizing repeater placement in long lines of a complex integrated circuit

• US 5,838,580 A
• Filed: 06/20/1996
• Issued: 11/17/1998
• Est. Priority Date: 06/20/1996
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Srivatsa, Chakra R.
• Primary Examiner(s): Voeltz, Emanuel Todd
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/667,908
• Time in Patent Office: 880 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578
• US Class Current: 716/114
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method includes operating a general purpose computer system to minimize signal-propagation delay time of a long line of a simulated circuit. A design engineer empirically derives two rule bases, the first of which determines whether to divide the long line into two or more segments by inserting repeater amplifiers into a long line to minimize the propagation delay through the line. The second rule base relates optimum amplifier size for driving long lines to line length. These rule bases are stored in a main memory of the computer system. The computer system is configured to apply the first rule base to the long line to determine whether to divide the long line into two or more segments by inserting repeater amplifiers, and to apply the second rule base to optimize the size of each of the repeater amplifiers. The resulting long line, segmented by size-optimized repeater amplifiers, provides minimal signal-propagation delay.

Claims

1. A method of operating a general-purpose computer system to minimize a time delay required for a signal to propagate between a first node and a second node of an integrated circuit, wherein a simulation of the integrated circuit is stored as circuit data in a first region of memory in the computer system, the method comprising:

analyzing the circuit data in the first region of memory to obtain signal-propagation-speed characteristics for a conductor connected between the first and second nodes;

generating a first simulated time delay representing a time required for the signal to propagate between the first and second nodes over said conductor;

deciding, based on the signal-propagation-speed characteristics of the conductor, whether separating the conductor into line segments, each of the line segments being separated from another of the line segments by a repeater amplifier, decreases the time required for the signal to propagate between the first and second nodes; and

indicating how many of the line segments are required to minimize the time delay required for said signal to propagate between said first node and said second node if separating the conductor into the plurality of segments decreases the time required for the signal to propagate between the first and second nodes.

2. The method of claim 1, wherein the signal-propagation-speed characteristics include resistance and capacitance.

3. The method of claim 1, wherein the signal-propagation-speed characteristics include a length of the conductor.

4. The method of claim 1, further comprising generating an optimum size of the repeater amplifier.

5. The method of claim 4, wherein the repeater amplifier includes an amplifier stage having a delay period, and wherein said generating the optimum size of the repeater amplifier comprises:

generating a first delay period associated with fabricating the amplifier of a first size X;

generating a second delay period associated with fabricating the amplifier of a second size fx where f is a taper factor;

providing a delay difference by subtracting the second delay period from the first delay period; and

comparing the delay difference with the delay period.

6. The method of claim 1, wherein the integrated circuit includes a third node connected to the first and second nodes via a second conductor, the first-mentioned conductor and the second conductor forming first and second signal paths between the first and second nodes and the first and third nodes, respectively, and wherein the signal-propagation-speed characteristics of the first conductor are determined in part by signal-propagation-speed characteristics of the second conductor.

7. The method of claim 6, wherein the signal-propagation-speed characteristics of the second conductor include a capacitance value corresponding to the second conductor.

8. The method of claim 6, further comprising displaying the second simulated time delay.

9. The method of claim 1, wherein each of the segments has an associated segment delay time, the method further comprising generating a second simulated time delay between the first and second nodes, the second simulated time delay being a sum of the segment delay times.

10. A method of operating a general-purpose computer system to minimize a simulated time delay required for a signal to propagate between a first node and a second node on a simulated circuit stored as circuit data in a first region of a memory in the computer system, the method comprising:

creating a first rule base for determining an optimum number of segments in which to divide a conductor connected between the first and second nodes;

creating a second rule base for determining an optimum driver size for the conductor;

storing the first rule base in a second region of the memory and the second rule base in a third region of the memory;

analyzing the circuit data in the first region of the memory to generate an RC time constant of the conductor;

generating a signal-propagation delay associated with the conductor;

deciding, using the RC time constant and the first rule base, whether to separate the conductor into a plurality of line segments, wherein each line segment in said plurality of line segments is separated from another line segment in said plurality of line segments by a repeater amplifier;

indicating how many of the line segments are required to minimize the time delay required for said signal to propagate between said first node and said second node if separating the conductor into the plurality of line segments decreases the time required for the signal to propagate between the first and second nodes; and

generating an optimum size for each repeater amplifier using the first rule base.

11. The method of claim 10, wherein each repeater amplifier has a stage delay period, and wherein optimizing the size of the repeater amplifier comprises:

generating a first delay period associated with fabricating the amplifier of a first size X;

generating a second delay period associated with fabricating the amplifier of a second size fx where f is a taper factor;

providing a delay difference by subtracting the second delay period from the first delay period; and

comparing the delay difference with the stage delay period.

12. The method of claim 10, wherein the integrated circuit includes a third node connected to the first and second node via a second conductor, the first-mentioned conductor and the second conductor forming first and second signal paths between the first and second nodes and the first and third nodes, respectively, the method further comprising:

analyzing the circuit data in the first region of memory to determine a capacitance of the second signal path;

representing the second signal path as a lumped capacitance connected to the first node;

simulating a repeater amplifier inserted at a point in the first signal path, the repeater amplifier dividing the first signal path into first and second signal-path segments; and

generating the respective time delays associated with the first and second signal-path segments and the simulated repeater amplifier;

wherein a new simulated time delay is the sum of the respective time delays associated with the first and second signal-path segments and the simulated repeater amplifier.

13. The method of claim 12, wherein the point is a midpoint of the first signal path.

14. The method of claim 13, wherein the midpoint divides the first signal path such that the first and second signal-path segments have approximately equal second and third RC time constants.

15. The method of claim 12, wherein the new simulated time delay is generated using a look-up table configured to relate signal propagation delay to amplifier and line segment characteristics.

16. The method of claim 10, wherein the second rule base is stored as a look-up table.

17. The method of claim 10, wherein the first rule base is stored as a look-up table.