Switching system having means for congestion control by monitoring packets in a shared buffer and by suppressing the reading of packets from input buffers
First Claim
Patent Images
1. A switching system connected to a plurality of input lines and a plurality of output lines, comprising:
- a plurality of input buffers provided for said input lines;
a plurality of input buffer control circuits corresponding to said input buffers, each input buffer control circuit writes a packet arriving at one of said input lines in one of said input buffers and reads said packet from said one input buffers, said packet being distributed to one of said output lines as a destination;
a switch which temporarily stores packets read from the plurality of input buffers in a shared buffer, and distributes each packet to one of said output lines determined as a destination by header information of said packet;
a monitor circuit which monitors a storage state of packets in said shared buffer on a destination output line basis, and generates congestion control information representing a congested output line; and
a congestion notifying circuit which notifies each of said input buffer control circuits of said congestion control information,wherein each of said input buffer control circuits decides whether to read said packet from said input buffer in accordance with said congestion control information.
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Abstract
In a switching system connected between a plurality of input lines and a plurality of output lines, destinations of a plurality of cells incoming from the plurality of input lines are monitored to detect an output line in a congestion state. Upon detection of the output line in an congestion state, congestion information indicating the output line in the congestion state is generated and added to the output cells. An input buffer control circuit derives the congestion information from the received cell, and performs buffering of a cell or cells in an input buffer, which cells are distributed to the output line in the congested state, among cells input from the input line.
164 Citations
42 Claims
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1. A switching system connected to a plurality of input lines and a plurality of output lines, comprising:
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a plurality of input buffers provided for said input lines; a plurality of input buffer control circuits corresponding to said input buffers, each input buffer control circuit writes a packet arriving at one of said input lines in one of said input buffers and reads said packet from said one input buffers, said packet being distributed to one of said output lines as a destination; a switch which temporarily stores packets read from the plurality of input buffers in a shared buffer, and distributes each packet to one of said output lines determined as a destination by header information of said packet; a monitor circuit which monitors a storage state of packets in said shared buffer on a destination output line basis, and generates congestion control information representing a congested output line; and a congestion notifying circuit which notifies each of said input buffer control circuits of said congestion control information, wherein each of said input buffer control circuits decides whether to read said packet from said input buffer in accordance with said congestion control information.
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2. A switching system connected to a plurality of input lines and a plurality of output lines, comprising:
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a plurality of input buffers provided for said input lines; a plurality of input buffer control circuits corresponding to said input buffers, each input buffer control circuit writes a packet arrived at one of said input lines in one of said input buffers and reads said packet from said one input buffer, said packet being distributed to one of said output lines as a destination; a switch which temporarily stores packets read from the plurality of input buffers in a shared buffer, and distributes each packet to one of said output lines determined as a destination by header information of said packet; a monitor circuit which monitors a storage state of packets in said shared buffer on a destination output line basis, and generates congestion control information representing a congested output line; and a congestion notifying circuit which notifies each of said input buffer control circuits of said congestion control information, wherein each of said input buffer control circuits decides whether to read said packet from said input buffer in accordance with said congestion control information, wherein said switch comprises; a multiplexer which multiplexes packets read from said plurality of input buffers and outputs a multiplexed packet, a shared buffer control circuit which writes each packet outputted from said multiplexer in said shared buffer in accordance with the header information of the packet, and reads each packet from said shared buffer in a predetermined order, and a demultiplexer which distributes packets read from said shared buffer to corresponding output lines, wherein said shared buffer control circuit monitors the storage state of packets in said shared buffer and generates said congestion control information. - View Dependent Claims (3, 4, 5, 6, 7, 8, 27, 28, 29, 30)
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9. A switching system comprising:
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a switch having a plurality of input ports and a plurality of output ports for causing a packet input from one of said input ports to be distributed to one of said output ports determined as a destination by header information of the packet; and at least one multiplexer/demultiplexer circuit which multiplexes input packets arriving from a plurality of input lines, inputs multiplexed packets into one of said input ports of said switch, and distributes an output packet received from one of said output ports of said switch one of a plurality of output lines, wherein said multiplexer/demultiplexer circuit includes an input buffer for temporarily storing said multiplexed input packets, and an input buffer control circuit which writes a packet into said input buffer and reads said packet to said input ports from said input buffer; wherein said switch includes a congestion notifying circuit which detects a storage state of packets in said switch for each of said output lines, generates congestion control information indicating an excessive storage of packets relative to a particular output line, and notifies said input buffer control circuit of said congestion control information; and wherein said input buffer control circuit suppresses reading, from said input buffer, of a packet to be distributed to said particular output line which is determined as a congested output line by said congestion control information.
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10. A switching system comprising:
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a switch having a plurality of input ports and a plurality of output ports for causing a packet input from one of said input ports to be distributed to one of said output ports determined as a destination by header information of the packet; and at least one multiplexer/demultiplexer circuit which multiplexer input packets arriving from a plurality of input lines, inputs multiplexed packets into one of said input ports of said switch, and distributes an output packet received from one of said output ports of said switch to one of a plurality of output lines, wherein said multiplexer/demultiplexer circuit includes an input buffer for temporarily storing said multiplexed input packets, and an input buffer control circuit which writes a packet into said input buffer and reads said packet to said input ports from said input buffer; wherein said switch includes a congestion notifying circuit which detects a storage state of packets in said switch for each of said output lines, generates congestion control information indicating an excessive storage of packets relative to a particular output line, and notifies said input buffer control circuit of said congestion control information; wherein said input buffer control circuit suppresses reading, from said input buffer, of a packet to be distributed to said particular output line which is determined as a congested output line by said congestion control information; and wherein said multiplexer/demultiplexer circuit includes a multiplexer circuit for multiplexing packets transmitted at a speed v from N input lines and outputting a multiplexed packet at a speed N×
v and a demultiplexer circuit for periodically causing an output packet, at the speed N×
v, received from one of the output ports of said switch to be distributed to a corresponding one of N output lines and outputs said output packet to the corresponding output line at the speed v. - View Dependent Claims (31, 32, 33, 35, 36, 37)
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11. A switching system comprising:
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a switch having a plurality of input ports and a plurality of output ports for causing a packet input from one of said input ports to be distributed to one of said output ports determined as a destination by header information of the packet; and at least one multiplexer/demultiplexer circuit which multiplexer input packets arriving from a plurality of input lines, inputs multiplexed packets into one of said input ports of said switch, and distributes an output packet received from one of said output ports of said switch to one of a plurality of output lines, wherein said multiplexer/demultiplexer circuit includes an input buffer for temporarily storing said multiplexed input packets, and an input buffer control circuit which writes a packet into said input buffer and reads said packet to said input ports from said input buffer; wherein said switch includes a congestion notifying circuit which detects a storage state of packets in said switch for each of said output lines, generates congestion control information indicating an excessive storage of packets relative to a particular output line, and notifies said input buffer control circuit of said congestion control information; wherein said input buffer control circuit suppresses reading, from said input buffer, of a packet to be distributed to said particular output line which is determined as a congested output line by said congestion control information; wherein said switch comprises; an intra-switch multiplexer circuit which multiplexes packets inputted from said plurality of input ports and outputs a multiplexed packet, a shared buffer which temporarily stores said multiplexed packet from said intra-switch multiplexer circuit, a shared buffer control circuit which writes each output packet in said shared buffer by adding each output packet to one of a plurality of variable length logical queues formed in correspondence with each output port, in accordance with header information of each output packet output from said intra-switch multiplexer circuit, and reads a packet by accessing each queue in a predetermined order, and a demultiplexer circuit which distributes a packet read from said shared buffer to a corresponding one of said plurality of output ports, wherein said congestion notifying circuit detects the number of packets in each of said queues in said shared buffer and generates said congestion control information. - View Dependent Claims (12, 13, 14, 15, 16, 17, 34)
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18. A switching system comprising:
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a switch having a plurality of input ports and a plurality of output ports for causing a packet input from one of said input ports to be distributed to one of said output ports determined as a destination by header information of the packet; and a plurality of multiplexer/demultiplexer circuits each corresponding to a pair of input and output ports, wherein each of said multiplexer/demultiplexer circuits comprises; a multiplexer which multiplexes input packets arriving from a plurality of input lines, an input buffer which temporarily stores multiplexed input packets, an input buffer control circuit which writes a packet into said input buffer and reads said packet to a corresponding input port from said input buffer, an output buffer which temporarily stores an output packet supplied from a corresponding output port, a demultiplexer which distributes an output packet read from said output buffer to one of a plurality of output lines, and an output buffer control circuit which writes an output packet into said output buffer, reads said output packet to said demultiplexer from said output buffer, and monitors a storage state of packets in said output buffer on an output line basis to generate congestion control information representing a congested output line in said output buffer, wherein said congestion control information is notified to input buffer control circuits of said multiplexing/demultiplexing circuits by a control information distribution circuit, and each of said input buffer control circuits suppresses reading from an input buffer a packet to be distributed to said congested output line identified by said congestion control information.
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19. A switching system comprising:
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a switch having a plurality of input ports and a plurality of output ports for causing a packet input from one of said input ports to be distributed to one of said output ports determined as a destination by header information of the packet; and a plurality of multiplexer/demultiplexer circuits each corresponding to a pair of input and output ports, wherein each of said multiplexer/demultiplexer circuits comprises; a multiplexer which multiplexes input packets arriving from a plurality of input lines, an input buffer which temporarily stores multiplexed input packets, an input buffer control circuit which writes a packet into said input buffer and reads said packet to a corresponding input port from said input buffer, an output buffer which temporarily stores an output packet supplied from a corresponding output port, a demultiplexer which distributes an output packet read from said output buffer to one of a plurality of output lines, and an output buffer control circuit which writes an output packet into said output buffer, reads said output packet to said demultiplexer from said output buffer, and monitors a storage state of packets in said output buffer on an output line basis to generate congestion control information representing a congested output line in said output buffer, wherein said congestion control information is notified to input buffer control circuits of said multiplexing/demultiplexing circuits by a control information distribution circuit, and each of an input buffer control circuits suppresses reading from said input buffer a packet to be distributed to said congested output line identified by said congestion control information; and wherein each output buffer control circuit writes an output packet in said output buffer by adding said output packet to each variable length logical queue formed for each output line, in accordance with header information of said output packet, counts the number of stored packets in each queue, compares the number of counted packets with a predetermined threshold value, and generates said congestion control information. - View Dependent Claims (38, 39, 40, 41)
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20. A switching system comprising:
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a switch having a plurality of input ports and a plurality of output ports for causing a packet input from one of said input ports to be distributed to one of said output ports determined as a destination by header information of the packet; and a plurality of multiplexer/demultiplexer circuits each corresponding to a pair of input and output ports, wherein each of said multiplexer/demultiplexer circuits comprises; a multiplexer which multiplexes input packets arriving from a plurality of input lines, an input buffer which temporarily stores multiplexed input packets, an input buffer control circuit which writes a packet into said input buffer and reads said packet to a corresponding input port from said input buffer, an output buffer which temporarily stores an output packet supplied from a corresponding output port, a demultiplexer which distributes an output packet read from said output buffer to one of a plurality of output lines, and an output buffer control circuit which writes an output packet into said output buffer, reads said output packet to said demultiplexer from said output buffer, and monitors a storage state of packets in said output buffer on an output line basis to generate congestion control information representing a congested output line in said output buffer, wherein said congestion control information is notified to input buffer control circuits of said multiplexing/demultiplexing circuits by a control information distribution circuit, and each of an input buffer control circuits suppresses reading from said input buffer a packet to be distributed to said congested output line identified by said congestion control information; and wherein said control information distribution circuit includes a congestion information distribution switch connected to said plurality of multiplexer/demultiplexer circuits for parallel distribution of said congestion control information collected from each output buffer control circuit to said plurality of input buffer control circuits.
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21. The switching system comprising:
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a switch having a plurality of input ports and a plurality of output ports for causing a packet input from one of said input ports to be distributed to one of said output ports determined as a destination by header information of the packet; and a plurality of multiplexer/demultiplexer circuits each corresponding to a pair of input and output ports, wherein each of said multiplexer/demultiplexer circuits comprises; a multiplexer which multiplexes input packets arriving from a plurality of input lines, an input buffer which temporarily stores multiplexed input packets, an input buffer control circuit which writes a packet into said input buffer and reads said packet to a corresponding input port from said input buffer, an output buffer which temporarily stores an output packet supplied from a corresponding output port, a demultiplexer which distributes an output packet read from said output buffer to one of a plurality of output lines, and an output buffer control circuit which writes an output packet into said output buffer, reads said output packet to said demultiplexer from said output buffer, and monitors a storage state of packets in said output buffer on an output line basis to generate congestion control information representing a congested output line in said output buffer, wherein said congestion control information is notified to input buffer control circuits of said multiplexing/demultiplexing circuits by a control information distribution circuit, and each of an input buffer control circuits suppresses reading from said input buffer a packet to be distributed to said congested output line identified by said congestion control information; and wherein each multiplexer/demultiplexer circuit includes a first circuit which adds said congestion control information to an input packet read from said input buffer; and wherein said control information distribution circuit includes a second circuit which derives said congestion control information from each input packet at said switch and a third circuit which notifies each input buffer control circuit of said congestion control information. - View Dependent Claims (22)
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23. The switching system comprising:
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a switch having a plurality of input ports and a plurality of output ports for causing a packet input from one of said input ports to be distributed to one of said output ports determined as a destination by header information of the packet; and a plurality of multiplexer/demultiplexer circuits each corresponding to a pair of input and output ports, wherein each of said multiplexer/demultiplexer circuits comprises; a multiplexer which multiplexes input packets arriving from a plurality of input lines, an input buffer which temporarily stores multiplexed input packets, an input buffer control circuit which writes a packet into said input buffer and reads said packet to a corresponding input port from said input buffer, an output buffer which temporarily stores an output packet supplied from a corresponding output port, a demultiplexer which distributes an output packet read from said output buffer to one of a plurality of output lines, and an output buffer control circuit which writes an output packet into said output buffer, reads said output packet to said demultiplexer from said output buffer, and monitors a storage state of packets in said output buffer on an output line basis to generate congestion control information representing a congested output line in said output buffer, wherein said congestion control information is notified to input buffer control circuits of said multiplexing/demultiplexing circuits by a control information distribution circuit, and each of an input buffer control circuits suppresses reading from said input buffer a packet to be distributed to said congested output line identified by said congestion control information; and wherein said switch comprises; an intra-switch multiplexer circuit which multiplexes packets input from said plurality of input ports and outputs a multiplexed packet; a shared buffer which temporarily stores said multiplexed packet from said intra-switch multiplexer circuit, a shared buffer control circuit which writes each output packet in said shared buffer by adding each output packet to a variable length logical queue formed in correspondence with each output port, in accordance with header information of each output packet output from said intra-switch multiplexer circuit, and reads a packet by accessing each queue in a predetermined order, and a demultiplexer circuit for causing a packet read from said shared buffer to be distributed to a corresponding one of said plurality of output ports.
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24. A switching system connected to a plurality of input lines and a plurality of output lines, comprising:
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a plurality of input buffers provided for said input lines; a plurality of input buffer control circuits corresponding to said input buffers, each input buffer control circuit writes a packet arriving at one of said input lines in one of said input buffers and reads said packet from said one input buffer, said packet being distributed to one of said output lines as a destination; a switch which temporarily stores packets read from the plurality of input buffers in a shared buffer, and distributes each packet to one of said output lines determined as a destination by header information of said packet; a monitor circuit which monitors a storage state of packets in said shared buffer on a destination output line basis, and generates congestion control information representing a congested output line; and a congestion notifying circuit which notifies each of said input buffer control circuits of said congestion control information, wherein each of said input buffer control circuits decides whether to read said packet from said input buffer in accordance with said congestion control information; and wherein a packet transferred from each input line to each said output line is a fixed length packet of an asynchronous transfer mode.
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25. The switching system comprising:
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a switch having a plurality of input ports and a plurality of output ports for causing a packet input from one of said input ports to be distributed to one of said output ports determined as a destination by header information of the packet; and at least one multiplexer/demultiplexer circuit which multiplexer input packets arriving from a plurality of input lines, inputs multiplexed packets into one of said input ports of said switch, and distributes an output packet received from one of said output ports of said switch to one of a plurality of output lines, wherein said multiplexer/demultiplexer circuit includes an input buffer for temporarily storing said multiplexed input packets, and an input buffer control circuit which writes a packet into said input buffer and reads said packet to said input ports from said input buffer; wherein said switch includes a congestion notifying circuit which detects a storage state of packets in said switch for each of said output lines, generates congestion control information indicating an excessive storage of packets relative to a particular output line, and notifies said input buffer control circuit of said congestion control information; wherein said input buffer control circuit suppresses reading, from said input buffer, of a packet to be distributed to said particular output line which is determined as a congested output line by said congestion control information; and wherein a packet transferred from each input line to each output line is a fixed length packet (cell) of an asynchronous transfer mode (ATM).
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26. A switching system comprising:
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a switch having a plurality of input ports and a plurality of output ports for causing a packet input from one of said input ports to be distributed to one of said output ports determined as a destination by header information of the packet; and a plurality of multiplexer/demultiplexer circuits each corresponding to a pair of input and output ports, wherein each of said multiplexer/demultiplexer circuits comprises; a multiplexer which multiplexes input packets arriving from a plurality of input lines, an input buffer which temporarily stores multiplexed input packets, an input buffer control circuit which writes a packet into said input buffer and reads said packet to a corresponding input port from said input buffer, an output buffer which temporarily stores an output packet supplied from a corresponding output port, a demultiplexer which distributes an output packet read from said output buffer to one of a plurality of output lines, and an output buffer control circuit which writes an output packet into said output buffer, reads said output packet to said demultiplexer from said output buffer, and monitors a storage state of packets in said output buffer on an output line basis to generate congestion control information representing a congested output line in said output buffer, wherein said congestion control information is notified to input buffer control circuits of said multiplexing/demultiplexing circuits by a control information distribution circuit, and each of an input buffer control circuits suppresses reading from said input buffer a packet to be distributed to said congested output line identified by said congestion control information; and wherein a packet transferred from each input line to each output line is a fixed length packet of an asynchronous transfer mode.
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42. A switching system connected between a plurality of input lines and a plurality of output lines comprising:
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a plurality of input buffers corresponding to said input lines; a control circuit provided for each of said input buffers for controlling a read/write of a packet arriving at a corresponding input line from/to a corresponding one of said input buffers; a distributing circuit which temporarily stores a packet from each of said input buffers in a shared buffer and distributes said packet to one of said output lines in accordance with a destination output line determined by header information of the packet; a congestion information generating circuit which monitors a storage state of packets in said shared buffer on an output line basis to generate congestion control information representing a congested output line; and a notifying circuit which notifies each of said control circuits of said congestion control information, wherein each of said control circuits suppresses reading from a corresponding input buffer a packet to be distributed to a congested output line in accordance to said congestion control information to control the packet storage state in said shared buffer.
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Specification
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Current AssigneeHitachi, Ltd.
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Original AssigneeHitachi, Ltd.
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InventorsEndo, Noboru, Takase, Akihiko, Takatori, Masahiro, Kozaki, Takahiko, Oguri, Yozo
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Primary Examiner(s)Olms, Douglas W.
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Assistant Examiner(s)HOM, SHICK C
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Application NumberUS08/633,306Time in Patent Office946 DaysField of Search370/389, 370/392, 370/395, 370/413, 370/414, 370/415, 370/416, 370/417, 370/418, 370/419, 370/428, 370/229, 370/230, 370/235, 370/412, 370/398US Class Current370/389CPC Class CodesH04L 12/5601 Transfer mode dependent, e....H04L 2012/5635 Backpressure, e.g. for ABRH04L 2012/5647 Cell lossH04L 2012/5679 Arbitration or schedulingH04L 2012/5681 Buffer or queue managementH04L 49/3081 ATM peripheral units, e.g. ...H04Q 11/0478 Provisions for broadband co...
