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Alignment of parity bits to eliminate errors in switching from an active to a standby processing circuit

  • US 5,838,698 A
  • Filed: 04/28/1995
  • Issued: 11/17/1998
  • Est. Priority Date: 04/28/1995
  • Status: Expired due to Fees
First Claim
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1. In a telecommunication apparatus having first and second processing devices where the first device processes sequential frames of data in an active mode and the second device operates in a standby mode ready to take over the processing of the frames of data from the first device, each of the sequential frames of data including a plurality of hierarchical generated parity bits, a method for aligning the parity bits during a change of processing of the frames of data from the first device to the second device comprising the steps of:

  • (a) determining whether the lowest rank parity bit in a first frame of data processed by the second device has the same polarity as the lowest rank parity bit processed by the first device during the first frame;

    (b) inverting the polarity of the lowest rank parity bit in the first frame of data processed by the second device if its polarity is not the same as the polarity of the corresponding parity bit processed by the first device during the first frame;

    (c) for parity bits processed by the second device, determining for each parity bit of a higher rank than the lowest rank parity bit if a polarity inversion of a lower ranked parity bit has occurred;

    (d) if the determination of step (c) is true for a one of the higher rank parity bits, selecting one inversion sequence from a set of inversion sequences to control inversions of the parity of said one parity bit, said selection of the one inversion sequence based on the number of inversions of lower rank parity bits.

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