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Secure communication by encryption/decryption of vector at PSK modulation/detection stage

  • US 5,838,797 A
  • Filed: 12/26/1995
  • Issued: 11/17/1998
  • Est. Priority Date: 12/26/1994
  • Status: Expired due to Fees
First Claim
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1. A secure communication system comprising:

  • a mapping circuit for mapping an N-bit symbol to a corresponding one of a predetermined number of vectors in a two-dimensional phase plane, where N is an integer equal to or greater than one;

    a first pseudorandom number generator for producing a first pseudorandom number varying in a range between 0 and 2π

    radian;

    means for producing a first sine-wave and a first cosine-wave in accordance with said first pseudorandom number;

    a first complex multiplier for complex, multiplying an output vector of said mapping circuit by the first sine-wave and the first cosine-wave;

    a first lowpass filter circuit for lowpass-filtering an output vector of said first complex multiplier;

    a first oscillator for producing a carrier;

    a quadrature modulator for quadrature-modulating said carrier with the lowpass-filtered vector for transmission;

    a second oscillator for producing a local carrier having a same frequency as the quadrature-modulated carrier;

    a quadrature detector for receiving the quadrature-modulated carrier and quasi-synchronously quadrature-detecting the received carrier with said local carrier;

    a second lowpass filter circuit for lowpass-filtering an output vector of said quadrature detector;

    a sampling circuit for sampling the lowpass-filtered output vector in response to a sampling pulse;

    a second pseudorandom number generator for producing a second pseudorandom number varying in a range between 0 and 2π

    radian, said second pseudorandom number being identical in magnitude to, but opposite in sign to said first pseudorandom number;

    means for producing a second sine-wave and a second cosine-wave in accordance with said second pseudorandom number;

    a second complex multiplier for complex-multiplying an output vector of said sampling circuit by the second sine-wave and the second cosine-wave;

    a quadrature demodulator for detecting a phase error of said local carrier with respect to the quadrature-modulated carrier and quadrature-demodulating an output vector of said second complex multiplier with the detected phase error; and

    means for estimating a phase error of an output vector of said quadrature demodulator with respect to said N-bit symbol and producing therefrom a timing signal and applying the timing signal to said sampling circuit as said sampling pulse.

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