System and method for simulation of computer systems combining hardware and software interaction
First Claim
1. A system for testing and analyzing electronic systems, including a target microprocessor and simulated target circuitry, and accompanying target program to be executed on the target microprocessor, the system comprising:
- a memory storing a plurality of computer instructions, said computer instructions including the target program;
a processor emulator employing a hardware device for emulating the target microprocessor, said processor emulator coupled to said memory to execute said computer instructions;
a hardware simulator coupled to said processor emulator to simulate the target circuitry; and
a communications interface to control communication between said processor emulator and said hardware simulator, said processor emulator communicating with said memory to receive said computer instructions from said memory, and said processor emulator communicating with said hardware simulator using said communications interface only when an event requires interaction of the target program with the target circuitry.
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Accused Products
Abstract
A system for simulation of target electronic systems combining interacting elements of hardware and executing software, in part by physical emulation means and in part by abstract software simulation. A processor emulator is coupled to a hardware simulator by a communications link. The processor emulator provides the functionality of the target microprocessor while the hardware simulator simulates additional target circuitry. The processor emulator is coupled to a memory containing the target program. Most computer instructions in the target program do not require interaction with the target circuitry simulated on the hardware simulator. However, when a computer instructions requires the interaction of the target microprocessor and the target circuitry, a communications link control the communication between the target microprocessor and the target circuitry. The various components of the system can be coupled together via a conventional computer network. A translator/mapper translates the computer data requiring the interaction between the target microprocessor and the target circuitry from the data format of the emulator to the data format of the hardware simulator. The translated data is then mapped to a set of simulated pins on a processor model shell in the hardware simulator.
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Citations
62 Claims
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1. A system for testing and analyzing electronic systems, including a target microprocessor and simulated target circuitry, and accompanying target program to be executed on the target microprocessor, the system comprising:
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a memory storing a plurality of computer instructions, said computer instructions including the target program; a processor emulator employing a hardware device for emulating the target microprocessor, said processor emulator coupled to said memory to execute said computer instructions; a hardware simulator coupled to said processor emulator to simulate the target circuitry; and a communications interface to control communication between said processor emulator and said hardware simulator, said processor emulator communicating with said memory to receive said computer instructions from said memory, and said processor emulator communicating with said hardware simulator using said communications interface only when an event requires interaction of the target program with the target circuitry. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A system for testing and analyzing electronic systems, including first and second target microprocessors and simulated target circuitry, and accompanying target program to be executed on each of the target microprocessors, the system comprising:
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a first memory storing a first set of computer instructions for the first target microprocessor, said first set of computer instructions including the target program for the first target microprocessor; a first processor emulator employing a hardware device for emulating the first target microprocessor, said first processor emulator coupled to said first memory to execute said first set of computer instructions; a second memory storing a second set of computer instructions for the second target microprocessor, said second set of computer instructions including the target program for the second target microprocessor; a second processor emulator employing a hardware device for emulating the second target microprocessor, said second processor emulator coupled to said second memory to execute said second set of computer instructions; a hardware simulator coupled to said first and second processor emulators to simulate the target circuitry; and a communications interface to control communication between said first and second processor emulators and said hardware simulator, said first and second processor emulators communicating with said first and second memories, respectively, to receive said first and second sets of computer instructions from said first and second memories, said first processor emulator communicating with said hardware simulator using said communications interface only when an event requires interaction of the target program for the first target microprocessor with the target circuitry, and said second processor emulator communicating with said hardware simulator using said communications interface only when an event requires interaction of the target program for the second target microprocessor with the target circuitry. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A system for testing and analyzing a electronic systems, including a target microprocessor and a target program to be executed on the target microprocessor, and simulated target circuitry simulated on a hardware simulator, the system comprising:
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a processor emulator employing a hardware device for emulating the target microprocessor, said processor emulator including a memory for storing and executing the target program; a processor model shell substituting for a processor model in the hardware simulator;
said processor model shell simulating activity of the pins of the target microprocessor;interaction detection means coupled to the processor emulator and said processor model shell, said interaction detection means recognizing, in cooperation with said processor emulator, when the target program needs to interact with the target circuitry in the hardware simulator; and a communication link coupling said processor model shell to said interaction detection means and coupling said interaction detection means to said processor emulator, whereby the system simulates the functional behavior of the target microprocessor executing target programs acting in conjunction with simulated target circuitry. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
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50. A system for testing and analyzing a computer system, including a processor emulator employing a hardware device for emulating a target microprocessor, said processor emulator including a memory for storing and executing a target program to be executed on the target microprocessor, and simulated target circuitry simulated on a hardware simulator, the system comprising:
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a software kernel communicating with the processor emulator and the hardware simulator, said software kernel recognizing, in cooperation with the processor emulator, when the target program needs to interact with the target circuitry in the hardware simulator; and a communication link coupling the hardware simulator to said software kernel and coupling said software kernel to the processor emulator, whereby the system simulates the functional behavior of the target microprocessor executing target programs acting in conjunction with simulated target circuitry.
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51. A system for testing and analyzing a computer system, including a processor emulator employing a hardware device for emulating a target microprocessor, said processor emulator including a memory for storing and executing a target program to be executed on the target microprocessor, and simulated target circuitry simulated on a hardware simulator, the system comprising:
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a software kernel communicating with the processor emulator and the hardware simulator, said software kernel recognizing, in cooperation with the processor emulator, when the executing target program needs to interact with the target circuitry in the hardware simulator, said target program and said hardware simulator otherwise executing in parallel; and a communication link coupling the hardware simulator to said software kernel and coupling said software kernel to the processor emulator, whereby the system simulates the functional behavior of the target microprocessor executing target program acting in conjunction with simulated target circuitry. - View Dependent Claims (52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62)
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Specification