Process for making a semiconductor MOS transistor

• US 5,840,611 A
• Filed: 07/23/1997
• Issued: 11/24/1998
• Est. Priority Date: 12/16/1993
• Status: Expired due to Term

• Current Assignee: Goldstar Electron Co., Ltd. (SK Hynix Inc.)
• Original Assignee: Goldstar Electron Co., Ltd. (SK Hynix Inc.)
• Inventors: Kim, Jae-Jeong, Lee, Chang-Jae
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/899,396
• Time in Patent Office: 489 Days
• Field of Search: 438/204, 438/301, 438/303, 438/306, 438/307, 438/585
• US Class Current: 438/307
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

The present invention provides a process for forming an MOS semiconductor device having an LDD structure, which includes a forming a gate electrode by first etching a conductive layer to a certain depth by an RIE process and by second etching the conductive layer by an isotropic plasma etching process. In forming the source/drain of the device, an n⁺ source/drain and an n^- source/drain are formed in a sequential manner. The gate line first is formed with its width over-sized compared with its channel length, and finally is formed to its final size.

Claims

1. A process for forming a MOS transistor having an LDD structure with at least a first impurity region and a second impurity region formed in a semiconductor substrate and a gate electrode of a first width, wherein the first impurity region has a higher inpurity concentration than the second impurity region and is spaced apart from a side of the gate electrode, the process comprising the steps of:

(a) forming an insulating layer on the semiconductor substrate;

(b) forming a conductive layer having a thickness on the insulating layer;

(c) forming an etch inhibition pattern on the conductive layer, wherein the etch inhibition pattern has a width greater than the first width;

(d) carrying out an anisotropic etching on the conductive layer using the etch inhibition pattern as a mask to remove a portion of the thickness of the conductive layer;

(e) carrying out an isotropic etching on the anisotropically etched conductive layer to form a gate electrode pattern, wherein the gate electrode pattern has concave sides and an upper portion of a second width greater than the first width;

(f) carrying out a first ion implantation for forming the first inpurity region in the semiconductor substrate, wherein the etch inhibition pattern and the gate electrode pattern having the upper portion of the second width are used as a first mask;

(g) removing the etch inhibition pattern after the first ion implantation;

(h) oxidizing e gate electrode pattern to form an oxide layer on the gate electrode pattern;

(i) removing the oxide layer for forming the gate electrode of the first width;

(j) carrying out a second ion implantation for forming the second impurity region in the semiconductor substrate, wherein the gate electrode is used as a second mask; and

(k) carrying out a heat treatment, wherein the LDD structure is formed.

2. The process of claim 1, wherein, after step (j), a second insulating layer is formed on the gate electrode and the semiconductor substrate.

3. The process of claim 1, wherein the insulating layer comprises a thermal oxide layer.

4. The process of claim 1, wherein the conductive layer comprises polysilicon.

5. The process of claim 1, wherein the anisotropic etching comprises reactive ion plasma etching.

6. The process of claim 1, wherein the isotropic etching comprises isotropic remote plasma chemical dry etching.

7. The process of claim 1, wherein the isotropic etching is carried out utilizing the insulating layer as an etch stop layer.

8. The process of claim 1, wherein the first ion implantation is carried out using As⁺ ions and under conditions of a concentration of about 3.0-6.0×

10¹⁵ ions/cm² and an acceleration energy of about 20-50 KeV.

9. The process of claim 1, wherein the second ion implantation is carried out using phosphorus ions and under conditions of a concentration of about 2.0-3.0×

10¹² ions/cm² and an acceleration energy of about 20-40 KeV.

10. A process for forming a transistor having an LDD structure with at least a first impurity region and a second impurity region formed in a semiconductor substrate and a gate electrode of a first width, wherein the first impurity region has a higher impurity concentration than the second impurity region and is spaced apart from a side of the gate electrode, the process comprising the steps of:

(a) forming a first insulating layer on the semiconductor substrate;

(b) forming a conductive layer having a thickness on the first insulating layer;

(c) forming an etch inhibition pattern on the conductive layer, wherein the etch inhibition pattern has a width greater than the first width;

(d) carrying out a first anisotropic etching on the conductive layer to remove a portion of the thickness of the conductive layer using the etch inhibition pattern as a mask;

(e) carrying out an isotropic etching on the anisotropically etched conductive layer to form a gate electrode pattern using the etch inhibition pattern as a mask, wherein the gate electrode pattern has concave sides and an upper portion including a tip portion, the upper portion having a second width greater than the first width;

(f) carrying out a first ion implantation in the semiconductor substrate for forming the first impurity region using the etch inhibition pattern and the gate electrode pattern as a first mask;

(g) removing the etch inhibition pattern after the first ion implantation;

(h) carrying out a second anisotropic etching on the gate electrode pattern for forming a gate electrode of the first width, wherein the tip portion of the gate electrode pattern is etched by the second anisotropic etching;

(i) carrying out a second ion implantation in the semiconductor substrate for forming the second impurity region using the gate electrode as a second mask;

(j) forming a second insulating layer on the first insulating layer and the gate electrode; and

(k) carrying out a heat treatment for forming the LDD structure.

11. The process of claim 10, wherein the first insulating layer is formed to thickness of about 100 Å

.

12. The process of claim 10, wherein the conductive layer is formed to a thickness over about 2500 Å

using phosphorus ions and applying a low pressure chemical vapor deposition method.

13. The process of claim 10, wherein the first anisotropic etching comprises a plasma anisotropic etching using a chlorine compound gas in a reactive ion etching system.

14. The process of claim 10, wherein the isotropic etching comprises an isotropic etching using a fluorine series gas and an isotropic remote plasma chemical dry etching method.

15. The process of claim 10, wherein the conductive layer is formed to a thickness of over about 2500 Å

and the first anisotropic etching etches about 1200 Å

of the first conductive layer.

16. The process of claim 10, wherein, after the anisotropic etching step, the conductive layer remains to a thickness of about 1300 Å

.

17. The process of claim 10, wherein the first insulating layer is used as an etch stop layer for the isotropic etching step.

18. The process of claim 10, wherein the second anisotropic etching is carried out by applying a general RIE polysilicon etching method.

19. The process of claim 10, wherein the heat treatment is carried out at a temperature of about 870°

C.